Shift Register Noise Reduction for High-Resolution Displays
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Solution Overview
Problem
As the number of pixels in high-definition displays increases, the load on shift registers grows, leading to reduced driving ability and increased noise at the output terminal, which affects the display's performance.
Innovation Solution
A shift register design incorporating a series-connection transistor structure and timing control to reduce leakage current at the output phase, utilizing an input unit, pull-up unit, pull-up control unit, pull-down unit, pull-down control unit, noise reduction units, and specific transistor and capacitor configurations to manage clock signals and supply voltages, thereby minimizing noise and enhancing driving capability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of pixels is increased to achieve high definition, then the display resolution is improved, but the load on the shift register increases and the driving ability deteriorates
Solution Approach 1:
The shift register is divided into multiple stages, with each stage responsible for driving a specific portion of the gate lines. This segmentation distributes the driving load across multiple register stages, preventing any single stage from being overloaded by the increased pixel count in high-definition displays.
Solution Approach 2:
The patent modifies the circuit parameters of the shift register stages, including adjusting the width of driving transistors and optimizing the timing parameters of clock signals. These parameter changes enable each register stage to maintain sufficient driving capability despite the increased overall pixel density.
2Measurement precision
If the number of pixels is increased to achieve high definition, then the display resolution is improved, but the noise at the output terminal increases
Solution Approach 1:
The patent introduces intermediary circuit elements between the shift register output and the gate lines, including buffer circuits and level translation stages. These intermediary components act as mediators that isolate the register output from direct load variations and filter out noise generated by the increased pixel driving requirements.
Solution Approach 2:
The patent utilizes the increased current drive capability required for high pixel counts to advantageously reduce the impact of leakage currents and noise. By designing the output stage to provide higher drive currents, the relative impact of noise and leakage is reduced, effectively converting the challenge of high pixel density into an opportunity to improve signal integrity.
Data Source
AI summary
A shift register includes: an input unit, configured to provide an input signal to a first node; a pull-up unit, configured to provide a voltage of a first supply voltage terminal to an output terminal; a pull-up control unit, configured to provide the voltage of the first supply voltage terminal or a voltage of a second supply voltage terminal to a second node; a pull-down unit, configured to provide a third clock signal from a third clock signal terminal to the output terminal; a pull-down control unit, configured to provide the voltage of the first supply voltage terminal to the first node; a first noise reduction unit, configured to reduce electrical leakage of the input unit to the first node; and a second noise reduction unit, configured to reduce electrical leakage of the pull-down control unit to the first node.