Shift Register Noise Reduction for Display Gate Drive Signals
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Solution Overview
Problem
Current gate drive circuits in liquid crystal display panels face issues with noise reduction, particularly in the second dummy shift register, where the potential of the pull-up node cannot be lowered due to unconnected reset terminals, leading to body bias and incorrect signal provision during backward scanning.
Innovation Solution
Incorporating a noise reduction control circuit and a pull-up node noise reduction circuit within the shift register, which controls the potential of a noise reduction node and pull-up node respectively, to maintain a first level during gate drive signal output stages and reduce noise during output cutoff stages, thereby preventing prolonged transistor open states and ensuring correct signal provision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate drive circuit includes multiple stages of shift registers with dummy shift registers, then the gate drive signal can be generated for liquid crystal display panel scanning, but the unconnected output terminals of dummy shift registers cause noise and body bias that affect signal accuracy
Solution Approach 1:
The patent extracts the noise reduction function into a separate control circuit that specifically targets the pull-up node. The control circuit monitors the output stage and selectively connects the pull-up node to ground during the output cutoff period, removing the harmful noise and body bias effect without affecting the normal gate drive signal generation function of the shift register stages.
Solution Approach 2:
The patent introduces a control circuit as an intermediary between the shift register output and the pull-up node. This control circuit acts as a mediator that conditionally connects or disconnects the pull-up node based on the output stage state, preventing direct noise coupling while maintaining the necessary circuit functionality during active periods.
2Device complexity
If the pull-up node potential is not lowered during output cutoff stage, then the circuit structure remains simple, but the transistor remains in open state causing incorrect signal provision during backward scanning
Solution Approach 1:
The patent applies preliminary action by proactively lowering the pull-up node potential during the output cutoff stage, which occurs before the backward scanning operation. This preliminary noise reduction action prevents the transistor from remaining in an incorrect open state, ensuring that when backward scanning commences, the circuit is already in the correct state for accurate signal provision.
Solution Approach 2:
The patent implements periodic action by cyclically controlling the pull-up node potential based on the output stage timing. During each output cutoff stage, the control circuit periodically lowers the pull-up node potential, and during active output stages, it maintains normal operation. This periodic control ensures consistent signal accuracy across multiple scanning cycles without requiring permanent circuit modification.
Data Source
AI summary
A shift register, a method for driving the shift register and a display apparatus are provided. The shift register includes a noise reduction control circuit and a pull-up node noise reduction circuit. The noise reduction control circuit is connected with a first clock signal terminal that receives a first clock signal, a gate drive signal output terminal that outputs a gate drive signal, a noise reduction control terminal, and a noise reduction control node. The pull-up node noise reduction circuit is connected with the noise reduction control circuit, the noise reduction control terminal, and a pull-up node.