Shift Register Noise Reduction for GOA Circuit Stability
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Solution Overview
Problem
Conventional Gate Driver on Array (GOA) driving circuits face challenges in reducing power consumption and improving stability, particularly as LCD panel sizes increase and circuit complexity grows.
Innovation Solution
A shift register design with multiple input and output modules, noise reduction modules, and reset modules is introduced, which includes pull-up and pull-down nodes, reference potential terminals, and specific transistor and capacitor configurations to control signal outputs and reduce noise, enabling efficient power management and enhanced stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the degree of integration is increased to reduce external circuit welding, then the production capacity and integration degree improve, but the power consumption increases and stability decreases
Solution Approach 1:
The shift register is divided into multiple stages with each stage containing separate input modules, output modules, and reset modules. This segmentation allows independent control of each stage, enabling selective activation to reduce overall power consumption while maintaining high integration density on the array substrate.
Solution Approach 2:
The circuit employs periodic clock signals to control the operation of output modules and reset modules. By using periodic activation rather than continuous operation, the circuit achieves high integration and scanning capability while reducing average power consumption through duty cycle control.
2Productivity
If the degree of integration is increased to reduce external circuit welding, then the production capacity improves, but the system stability decreases
Solution Approach 1:
Reset modules are configured to preliminarily reset the state of each stage before signal transmission. This preliminary action ensures that each integrated stage starts from a known stable state, preventing error propagation through the highly integrated circuit and improving overall system reliability.
Solution Approach 2:
The circuit incorporates feedback mechanisms where output signals are monitored and used to control subsequent operations. This feedback ensures stable operation in the highly integrated structure by detecting and correcting deviations, maintaining system reliability despite increased integration complexity.
3Object-affected harmful factors
If more noise reduction modules are added, then the noise immunity improves, but the device complexity increases
Solution Approach 1:
Noise reduction functionality is merged into the existing input and output modules rather than being implemented as separate dedicated noise reduction circuits. The reset modules serve dual purposes of state initialization and noise filtering, reducing overall circuit complexity while maintaining strong noise immunity.
Solution Approach 2:
The reset modules and clock control circuits are designed to perform multiple functions including state initialization, signal synchronization, and noise filtering. This multi-functionality provides robust noise immunity without significantly increasing device complexity, as the same structural elements serve multiple protective and control roles.
Data Source
AI summary
The present disclosure provides a shift register, a GOA circuit, a display device, and a driving method. A shift register is provided which comprises: at least one input sub-circuit for charging a pull-up node; at least one output sub-circuit for outputting a respective clock signal; first reset sub-circuit(s) for pulling the potential of the respective signal output terminal down to a reference potential; a first noise reduction sub-circuit for performing noise reduction on the pull-up node through a signal input from the reference potential terminal; a second noise reduction sub-circuit for performing noise reduction on the pull-down node through a signal input from the reference potential terminal; and a second reset sub-circuit for controlling the potential of the pull-down node under control of a signal input from the reset clock signal input terminal.