Shift Register Noise Reduction Module for Gate Driver Signal Integrity

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Solution Overview

Problem

Noise interference occurs on the output end of a gate driving signal in display devices due to the inherent characteristics of thin film transistors, which can cause abnormal display even when the output transistor is supposed to be off, especially when the clock signal is at a high level.

Innovation Solution

A shift register design that includes an input module, an output module, a reset module, and noise reduction modules connected through a pull-up node, where the noise reduction modules are controlled to maintain a low-level signal at the pull-up node even when the clock signal is high, preventing noise interference by ensuring the output module does not provide a clock signal during high-level clock signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If thin film transistor switches are turned on row by row to complete data signal input, then the scanning driving function is achieved, but noise interference is generated on the output end when the clock signal is at high level during the output off-holding period

Engineering Contradiction:
Improvesignal integrityVSAvoidnoise interference
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The patent applies preliminary anti-action by introducing a noise reduction module that proactively counteracts the potential noise interference before it affects the output signal. The module includes a noise reduction transistor connected to the output end, which is controlled to turn on during the output off-holding period when the clock signal is at high level, thereby preemptively preventing noise from coupling into the output signal line.

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The noise reduction transistor serves as an intermediary element between the output module and the output signal line. It acts as a controlled connection that can selectively ground or discharge noise charges during critical periods, mediating the interaction between the clock signal and the output signal to prevent harmful noise coupling while maintaining normal signal transmission.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Use of energy by moving object

If the output transistor is kept off during the output off-holding period, then power consumption is reduced, but noise interference still occurs on the output end when the clock signal is at high level

Engineering Contradiction:
Improvepower consumptionVSAvoidnoise interference
Core Design Contradiction:
Use of energy by moving objectVSObject-affected harmful factors

Solution Approach 1:

The patent segments the output control function into two independent components: the output transistor that controls signal transmission during active periods, and the noise reduction transistor that specifically handles noise suppression during the off-holding period. This segmentation allows each transistor to be optimized for its specific function, with the noise reduction transistor activated only when needed to suppress noise, thereby minimizing overall power consumption while effectively addressing noise interference.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The noise reduction transistor operates periodically rather than continuously, being activated only during the output off-holding period when the clock signal is at high level and noise interference is most likely to occur. This periodic operation significantly reduces power consumption compared to keeping the transistor continuously on, while still providing effective noise suppression during the critical vulnerable periods.

Inventive Principle:
Principle #19Periodic action

Data Source

PatentUS12027088B2Shift register, gate driver circuit, and display device
Publication Date: 2024.07.02 TCL CHINA STAR OPTOELECTRONICS TECHNOLOGY CO LTD
  • US12027088B2 patent drawing
  • US12027088B2 patent drawing
  • US12027088B2 patent drawing

AI summary

A shift register, a gate driver circuit, and a display device are disclosed. In the shift register, when a pull-up node is at a low level, a third signal control end controls a conduction of a first noise reduction module and provides the pull-up node with a low-level signal of a first power supply end, so as to pull down a signal of the pull-up node to reduce noise. Therefore, an issue of noise interference on an output end of a gate driving signal is solved when a clock signal provided by a clock signal end is at a high level.