Shift Register Unit Noise Suppression via Segmented Sub-Circuits

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Solution Overview

Problem

Noise in the gate driving signal from shift register units can cause false activation of thin-film transistors, leading to light leakage and image quality issues like strobe or blur in display apparatuses.

Innovation Solution

A shift register unit circuit with a pull-up control sub-circuit, pull-up sub-circuit, pull-down control sub-circuit, pull-down sub-circuit, reset sub-circuit, and initialization sub-circuit, utilizing complementary clock signals to control potential levels and output signals, ensuring accurate gate driving signals are generated and maintained, thereby suppressing noise-induced errors.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If simple shift register unit is used, then device complexity is reduced, but noise in gate driving signal causes false activation of transistors leading to light leakage and image quality issues

Engineering Contradiction:
Improvegate driving signal accuracyVSAvoidshift register unit structure
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shift register unit is divided into multiple functional sub-circuits: pull-up control sub-circuit, pull-up sub-circuit, pull-down control sub-circuit, pull-down sub-circuit, reset sub-circuit, and initialization sub-circuit. Each sub-circuit performs a specific function in controlling the potential levels at different nodes, thereby managing complexity through functional segmentation while ensuring reliable noise suppression

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent introduces intermediate control nodes (pull-up node, first pull-down node, second pull-down node) that act as mediators between the input signal and the output gate driving signal. These intermediate nodes allow for staged control and suppression of noise, preventing false activation while maintaining signal integrity through the circuit

Inventive Principle:
Principle #24Intermediary (Mediator)

2Object-affected harmful factors

If noise suppression measures are added to shift register unit, then image quality is improved, but circuit structure becomes more complex

Engineering Contradiction:
Improvenoise-induced light leakageVSAvoidcircuit structure
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The circuit applies preliminary anti-action by using the pull-down control sub-circuit to proactively suppress noise at the pull-up node before it can cause false activation. The pull-down control sub-circuit receives clock signals and actively counteracts noise impulses, preventing light leakage and image quality issues before they occur

Inventive Principle:
Principle #9Preliminary anti-action

Solution Approach 2:

The initialization sub-circuit performs preliminary action by setting the potential levels of the pull-up node and pull-down nodes to predetermined states before the shift register unit begins normal operation. This preliminary initialization ensures that the circuit starts in a known stable state, preventing noise-induced errors from the outset

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10204696B2Shift register unit, gate drive circuit having the same, and driving method thereof
Publication Date: 2019.02.12 BOE TECHNOLOGY GROUP CO LTD
  • US10204696B2 patent drawing
  • US10204696B2 patent drawing
  • US10204696B2 patent drawing

AI summary

The present application discloses a shift register unit circuit including an input port for receiving an input signal, an output port for outputting a gate driving signal, a first clock input port for receiving a first clock signal, a second clock input port for receiving a second clock signal, a pull-up node, a first pull-down node, a second pull-down node, a pull-up control sub-circuit connected to the input port and the pull-up node, a pull-up sub-circuit connected to the first clock input port and the pull-up node, a pull-down control sub-circuit connected to the first clock input port, a pull-down sub-circuit connected to the first pull-down node and the second pull-down node, a reset sub-circuit receiving a reset signal to control the potential level at the second pull-down node, and an initialization sub-circuit configured to receive an enabling signal for pulling-down the potential level at the second pull-down node.