Shift Register Unit Noise Suppression in Gate Driving Circuits
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Solution Overview
Problem
The existing gate driving circuits in TFT-LCDs have high power consumption and are prone to noise due to their design and require additional virtual shift register units, which complicates wiring and increases power consumption further.
Innovation Solution
A shift register unit and gate driving circuit configuration that includes an input module, output module, pull-down driving module, pull-down module, and reset module, which effectively suppresses noise by continuously discharging nodes and reduces power consumption by eliminating the need for virtual shift register units, thereby simplifying wiring.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If virtual shift register units are added to enable the gate driving circuit to operate normally, then the gate driving circuit can function properly, but the wiring becomes more complex and power consumption increases
Solution Approach 1:
The patent extracts and eliminates the virtual shift register units from the gate driving circuit. By removing these unnecessary components, the circuit achieves normal operation without requiring additional virtual units, thereby simplifying the wiring structure and reducing power consumption while maintaining reliability
Solution Approach 2:
The patent makes the shift register units universal by designing them with identical structures throughout the circuit. Each shift register unit can perform the same functions without requiring special virtual units, allowing the circuit to operate normally with standardized components that simplify wiring and reduce complexity
2Reliability
If virtual shift register units are added to enable the gate driving circuit to operate normally, then the gate driving circuit can function properly, but power consumption increases
Solution Approach 1:
The patent removes the virtual shift register units that were causing excessive power consumption. By extracting these unnecessary components, the circuit maintains normal operation while significantly reducing the power consumption associated with driving additional virtual units and their associated wiring
Solution Approach 2:
The patent discards the virtual shift register units that were consuming unnecessary power. By eliminating these redundant components, the circuit recovers power efficiency while maintaining functional reliability through the optimized shift register unit design
3Ease of manufacture
If the existing shift register unit structure is used, then the gate driving circuit can be implemented, but noise is generated and power consumption is high
Solution Approach 1:
The patent changes the operating parameters and structure of the shift register units. By modifying the circuit configuration and signal levels, the patent achieves lower power consumption and reduced noise generation while maintaining ease of manufacture through standardized TFT-based implementation
Solution Approach 2:
The patent converts the potentially harmful effects of noise and high power consumption into benefits by optimizing the shift register unit design. The modified structure reduces noise interference and power consumption while maintaining manufacturability, turning the original drawbacks into improved performance characteristics
Data Source
AI summary
There are provided a shift register unit, a gate driving circuit and a display apparatus, which are configured to suppress interference noise due to a change of an alternating current clock signal and enhance stability of the shift register unit. The shift register unit comprises: an input module configured to charge a pull-up node in response to the input signal; a pull-down module configured to provide the low voltage signal to the pull-up node and the output terminal in response to a voltage signal of the pull-down node; a pull-down driving module configured to charge a pull-down node in response to the first clock signal and the second clock signal and discharge the pull-down node in response to the voltage signal of the pull-up node; an output module configured to provide a first clock signal to an output terminal in response to a voltage signal of the pull-up node; and a reset module configured to discharge the output terminal in response to the second clock signal.


