Single Clock Shift Register Non-Overlap Buffer
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Solution Overview
Problem
The overlap of output signals in traditional single clock shift registers affects the precision of data sampling and image quality in Active Matrix Liquid Crystal Displays (AMLCDs), leading to reduced image quality and inaccurate TFT on/off times.
Innovation Solution
A single clock driven shift register with multiple stages, each comprising a latch unit, a logic unit, and a non-overlap buffer with three serially connected inverters, which delays the output signal to prevent overlap between neighboring stages, ensuring precise sampling and improved image quality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If a traditional single clock driven shift register is used, then the circuit structure is simple, but the output signals of neighboring stages overlap which reduces sampling precision and image quality
Solution Approach 1:
The shift register stage is segmented into distinct functional units: a latch unit for signal storage, a logic unit for signal processing, and a non-overlap buffer unit for timing control. This segmentation allows each unit to perform its specific function independently, preventing signal overlap while maintaining overall circuit functionality.
Solution Approach 2:
A non-overlap buffer unit comprising three inverters is introduced as an intermediary between the latch unit and the next stage. This buffer acts as a mediator that delays the output signal, ensuring that signals from neighboring stages do not overlap. The buffer unit receives the output signal from the latch unit, applies a deliberate delay through the inverter chain, and then outputs the delayed signal to the next stage, thereby preventing the harmful overlap effect.
2Reliability
If the output signal is delayed to prevent overlap, then sampling precision is improved, but the circuit complexity increases due to additional buffer units
Solution Approach 1:
The timing parameter of the output signal is changed by introducing a deliberate delay through the non-overlap buffer. By adjusting the number of inverters in the buffer chain (three inverters in this embodiment), the signal delay is optimized to prevent overlap while maintaining synchronization with the clock signal. This parameter change ensures that the output signal transitions occur at the correct time, improving TFT operation accuracy.
Data Source
AI summary
A single clock driven shift register comprising multiple stages is provided. The (M)th stage comprises a latch unit, a logic unit, and a non-overlap buffer. The latch unit latches an input signal from the (M−1)th stage according to a clock signal. The logic unit connecting to an output terminal of the latch unit deals with an output signal of the latch unit and the clock signal with an NAND logic calculation. The non-overlap buffer connecting to the output terminal of the logic unit comprises at least three inverters connected in a serial, and an output signal of the first inverter coupled to the output terminal of the logic unit is input to an latch unit of the (M+1)th stage. Meanwhile, an output signal of the non-overlap buffer of the (M−1)th stage is input to the non-overlap buffer or the logic unit to delay the output signal of the non-overlap buffer.