Shift Register Using Non-Overlapping Clocks to Eliminate Through Current
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Solution Overview
Problem
Conventional shift registers in display devices experience issues with power consumption and erroneous operations due to through currents and noise, especially when using two-phase clock signals with overlapping on-level periods.
Innovation Solution
A shift register configuration using cascaded unit circuits with transistors of identical conduction type, operating on non-overlapping two-phase clock signals, includes an output control transistor, a precharge circuit, a reset signal generation circuit, and a discharge circuit to maintain output signals at predetermined levels without through current flow, achieved through the use of a reset signal generated by transistors and capacitors.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If a bootstrap circuit is used to output a clock signal without changing voltage level, then the clock signal can be output without voltage drop, but through current flows during certain periods causing increase in power consumption
Solution Approach 1:
The patent employs periodic action by using two-phase clock signals (CK1 and CK2) with non-overlapping high-level periods to control the conductance states of transistors. This periodic control ensures that transistors are turned on and off in sequence, preventing simultaneous conduction paths and thus eliminating through current while maintaining clock signal output capability.
Solution Approach 2:
The patent applies dynamics by making the transistor conductance states time-dependent through the use of two-phase clock signals. The transistors dynamically switch between on and off states based on the phase of clock signals, allowing the circuit to adapt its conductance profile over time to prevent through current while maintaining functionality.
2Ease of manufacture
If transistors of identical conduction type are used in the shift register, then manufacturing cost is reduced, but through current flows causing erroneous operations
Solution Approach 1:
The patent uses periodic action with two-phase non-overlapping clock signals to control transistor switching. This ensures that only one transistor is conducting at a time, preventing through current paths while maintaining the simplicity of using identical conduction type transistors throughout the circuit.
Solution Approach 2:
The patent implements feedback by using the output signal from one stage to control the reset signal generation in the same stage, and using clock signals to control transistor switching. This feedback mechanism ensures proper timing and prevents erroneous operations by coordinating transistor states based on previous outputs and clock phases.
3Device complexity
If output terminal is left floating during certain periods, then circuit complexity is reduced, but noise interference causes erroneous operations
Solution Approach 1:
The patent applies feedback by using the reset signal generation circuit that monitors the output signal state and generates appropriate reset signals. This feedback mechanism ensures that the output terminal is properly controlled and not left floating, preventing noise interference while maintaining circuit simplicity through the use of existing signal paths.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for low power consumption and stable operation by preventing through current flow and reducing noise interference, effectively fixing output signals at desired levels.
Implementation Method 1
the voltage potential at the node N1 becomes higher than VDD by function of a capacitor C1 provided between a gate terminal and a source terminal of the transistor T2 (a bootstrap effect)
Data Source
AI summary
In one embodiment of the present invention, a unit circuit of a shift register includes a bootstrap circuit configured with a transistor T1, a transistor T2 and a capacitor, a transistor T3, a transistor T4, and a reset signal generation circuit. By use of two-phase clock signals and whose high level periods do not overlap with each other, the reset signal generation circuit generates a reset signal which is at a high level in a normal state and changes to a low level when an input signal turns into the high level. During a period that the reset signal is at the high level, transistors T3 and T4 perform discharge of a node and pull-down of an output signal. Thus, it is possible to obtain a power-saving shift register that fixes an output signal at a low level in a normal state without allowing a through current to flow therein.