Shift Register With Non-Overlapping Signals For LCD Drivers
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Solution Overview
Problem
Conventional shift registers in LCDs suffer from signal overlap issues, leading to interference when used in gate and data drivers, which affects the accuracy of scanning and signal processing.
Innovation Solution
The proposed shift register design includes a plurality of units with specific switch circuits and inverters that manage clock and input signals to prevent signal overlap, ensuring non-overlapping effective signals and improved signal accuracy.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional shift register units are used in LCD gate and data drivers, then the structure is simple and easy to manufacture, but signal overlap occurs between adjacent shift register units causing interference and reducing scanning accuracy
Solution Approach 1:
The patent divides the clock signal input into two separate inputs (first clock signal input terminal and second clock signal input terminal) for each shift register unit. This segmentation allows adjacent units to receive non-overlapping clock phases, preventing signal overlap and interference while maintaining manufacturing feasibility through modular design
Solution Approach 2:
The patent introduces a phase control circuit as an intermediary between the clock signal source and the shift register units. This circuit generates phased clock signals that are distributed to different units in a controlled sequence, ensuring that adjacent units operate in non-overlapping time windows and eliminating signal interference
2Productivity
If multiple shift register units operate simultaneously in LCD drivers, then productivity and scanning speed are improved, but signal interference occurs due to overlapping output signals
Solution Approach 1:
The patent implements periodic clock signal distribution where each shift register unit receives clock signals at different phases of the periodic cycle. This ensures that while multiple units operate simultaneously for high productivity, their active periods are staggered in time, preventing signal overlap and interference
Solution Approach 2:
The patent uses a phase control circuit that preliminarily determines and assigns specific time windows for each shift register unit's operation. By pre-coordinating the activation timing of adjacent units before they operate, the system enables simultaneous operation without signal conflict, maintaining both high speed and signal integrity
Data Source
AI summary
An exemplary shift register (20) includes a plurality of shift register units (200) connected one by one. Each of the shift register units includes a clock signal input terminal (TS), a high level signal input terminal (VH), a low level signal input terminal (VL), an output terminal (VOUT), a reverse output terminal (VOUTB), a first input terminal (VIN1), a second input terminal (VIN2), a first common node (P1), a second common node (P2), a first switch circuit (31), a second switch circuit (32), a third switch circuit (33), a fourth switch circuit (34), a fifth switch circuit (35), a six switch circuit (36), a first inverter (37) connected between the first common node and the second common node, and a second inverter (39) connected between the output terminal and the reverse output terminal.