Shift Register Circuit for OLED Gate Drivers

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Solution Overview

Problem

Current gate driving circuits in OLED display devices are complex and cannot meet the requirements of high resolution and narrow borders, often resulting in output waveform anomalies.

Innovation Solution

A shift register unit circuit with a simplified structure, comprising sub-unit circuits and conduction control circuits, that generates and supplies gate driving signals by controlling node conduction based on input pulses, clock signals, and reset pulses, ensuring efficient signal output.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a simplified gate driving circuit structure is adopted, then device complexity is reduced, but output waveform anomalies occur

Engineering Contradiction:
Improvecircuit structure complexityVSAvoidoutput waveform quality
Core Design Contradiction:
Device complexityVSReliability

Solution Approach 1:

The gate driving circuit is divided into multiple independent shift register unit circuits, each capable of generating gate driving signals autonomously. Each unit contains separate input circuits, output circuits, and reset circuits that can be independently controlled, allowing the complex function to be distributed across multiple simpler modules rather than requiring a single complex circuit

Inventive Principle:
Principle #1Segmentation

2Ease of manufacture

If the gate driving circuit is simplified, then ease of manufacture is improved, but manufacturing precision deteriorates

Engineering Contradiction:
Improvecircuit fabrication simplicityVSAvoidsignal output accuracy
Core Design Contradiction:
Ease of manufactureVSManufacturing precision

Solution Approach 1:

The circuit incorporates preliminary reset actions through dedicated reset pulses that prepare the circuit state before signal generation. The reset circuit proactively clears previous states and ensures the circuit is in a known good state before operating, preventing waveform anomalies from previous operations from affecting current signal accuracy

Inventive Principle:
Principle #10Preliminary action

3Reliability

If a complex gate driving circuit is used, then output waveform quality is maintained, but device complexity increases

Engineering Contradiction:
Improveoutput waveform qualityVSAvoidcircuit structure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

Multiple functional circuits (input circuits, output circuits, reset circuits) are merged into a single integrated shift register unit circuit structure. The cascaded connection allows these circuits to work together cooperatively, achieving reliable waveform output through coordinated operation rather than requiring separate complex circuits for each function

Inventive Principle:
Principle #5Merging (Combining)

4Productivity

If the gate driving circuit is simplified, then productivity is improved, but signal output reliability deteriorates

Engineering Contradiction:
Improvesignal generation efficiencyVSAvoidsignal output quality
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

Each shift register unit circuit is self-contained with its own input, output, and reset circuits that can operate autonomously. The circuit serves itself by internally managing signal generation and reset operations without requiring external complex control mechanisms, maintaining high productivity while ensuring reliable signal output through self-regulation

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS11393405B2Shift register unit circuit and drive method, and gate driver and display device
Publication Date: 2022.07.19 HEFEI BOE ZHUOYIN TECH CO LTD
  • US11393405B2 patent drawing
  • US11393405B2 patent drawing
  • US11393405B2 patent drawing

AI summary

Provided are a shift register unit circuit and drive method, and a gate driver and a display device. The shift register unit circuit includes a first sub-unit circuit, a second sub-unit circuit, a third sub-unit circuit, and a fourth sub-unit circuit. Responsive to providing a corresponding input pulse and clock signal, the shift register unit circuit is configured output first, second, third, and fourth output signals. The shift register unit circuit is configured such that a fifth node is in conduction with a second node at least while the reset pulse is active.