Shift-Register Gate Driving for Narrow-Bezel OLED Displays
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Solution Overview
Problem
Existing OLED gate-driving circuits are complex and difficult to meet the demands of high-resolution displays with narrow frame borders due to their intricate structure, primarily comprising sense, scan, and connection circuits.
Innovation Solution
A redesigned shift-register unit with a first and second circuit, each having input and output circuits, and a blank-input circuit, including common-input and transport circuits, to control voltage levels and output signals, reducing complexity and enabling cascaded series connections for efficient gate-driving.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If existing OLED gate-driving circuits include sense unit circuit, scan unit circuit, and connection circuit, then the driving function is complete, but the circuit structure becomes very complex and chip area increases
Solution Approach 1:
The patent merges the sense unit circuit and scan unit circuit into a unified shift register structure. The sense signal input terminal and scan signal input terminal are integrated into the same circuit framework, where transistors serve dual functions for both sensing and scanning operations. This consolidation eliminates the need for separate dedicated circuits, thereby reducing overall circuit complexity and chip area while maintaining complete driving functionality.
Solution Approach 2:
The shift register unit is designed with multi-functional transistors that can operate in different modes. For example, the first transistor can function as a sensing transistor during sense operations and as a scanning transistor during scan operations. The same circuit nodes and components are reused for multiple purposes, which reduces the total number of components required and simplifies the overall circuit architecture.
2Manufacturing precision
If the Gate IC is designed with complex sub-circuits for high resolution display, then display resolution can be achieved, but the frame border becomes wider and narrow frame requirement cannot be met
Solution Approach 1:
The gate-driving circuit is divided into multiple shift register units that are cascaded together. Each shift register unit handles a specific portion of the display lines, allowing the driving function to be distributed across multiple smaller, more efficient modules. This segmentation enables high-resolution display capability while keeping each individual unit compact, thus reducing the overall frame border width.
3Adaptability or versatility
If the shift-register unit uses separate input circuits for first and second circuits, then each circuit can be independently controlled, but the number of transistors and clock signal lines increases
Solution Approach 1:
The blank-input circuit merges the control functions for both the first and second circuits into a unified structure. A single set of control signals is used to coordinate the operation of multiple circuits within the shift register unit. This consolidated control approach maintains independent controllability of individual circuits while significantly reducing the total number of transistors and clock signal lines required compared to completely separate control circuits.
Data Source
AI summary
A shift-register unit includes a first circuit including a first input circuit coupled via a first node to a first output circuit, and a second circuit including a second input circuit coupled via a second node to a second output circuit. The first input circuit is configured to control a voltage level of the first node in response to a first input signal. The first output circuit is configured to output a shift-register signal and a first output signal in response to the voltage level of the first node. The second input circuit is configured to control a voltage level of the second node in response to the first input signal. The second output circuit is configured to output a second output signal in response to the voltage level of the second node. The first input circuit includes a fifth transistor.


