Shift Register Unit for OLED Gate Driving Circuit
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current shift register units in OLED display technology require a large number of units to drive one row of pixels, occupying a significant area and increasing costs due to complex structures and high power consumption.
Innovation Solution
A shift register unit design that outputs multiple gate driving signals under the control of a single trigger signal, utilizing a simplified structure with transistors and capacitors to reduce the number of units needed and minimize power consumption, by adjusting control clock signals to manage voltage levels and prevent leakage currents.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional shift register units are used to drive one row of pixels, then the gate driving function is achieved, but the area occupied is large and the structure is complex
Solution Approach 1:
The shift register unit is designed to output multiple gate driving signals (G1, G2, G3, G4) simultaneously, allowing a single unit to drive multiple pixel groups. This multi-functionality reduces the total number of shift register units needed and simplifies the overall gate driving circuit structure while maintaining complete gate driving capability for all pixels in a row
Solution Approach 2:
Multiple gate driving signal output functions are merged into a single shift register unit. The unit integrates multiple output circuits that can generate different gate driving signals (G1-G4) with different voltage levels and timing characteristics, combining what would traditionally require separate units into one integrated structure
2Reliability
If conventional shift register units are used, then the gate driving function is achieved, but the power consumption is high
Solution Approach 1:
Different output circuits within the shift register unit are designed with tailored transistor configurations and voltage levels suited to their specific output requirements. Each output circuit (G1-G4) uses appropriately sized transistors and voltage levels matched to its specific driving needs, optimizing power consumption for each function rather than using a uniform high-power design throughout
Solution Approach 2:
The shift register unit generates multiple gate driving signals with different voltage levels (e.g., different high levels and low levels) to match the specific requirements of different pixel groups. By adjusting voltage parameters and timing characteristics for each output signal, the unit achieves efficient driving with reduced overall power consumption compared to conventional uniform signaling
3Reliability
If conventional shift register units are used, then the gate driving function is achieved, but the number of units required is large
Solution Approach 1:
Each shift register unit functions as a multi-output device capable of generating multiple gate driving signals (G1, G2, G3, G4) that can drive different groups of pixels simultaneously. This universal multi-functionality allows fewer units to cover the entire pixel row compared to conventional single-output units
Solution Approach 2:
The pixel row is divided into multiple groups that can be driven by different output signals from the same shift register unit. The segmentation of pixel groups combined with the multi-output capability allows efficient coverage of all pixels using a reduced number of shift register units
4Reliability
If conventional shift register units are used, then the gate driving function is achieved, but signal noise and current leakage increase
Solution Approach 1:
The shift register unit employs carefully designed transistor configurations and voltage level transitions that act as intermediaries to control signal propagation. The circuit design includes mechanisms to prevent unwanted current leakage between different output circuits and to minimize noise coupling, ensuring clean signal transmission to each pixel group
Data Source
AI summary
Embodiments of the present disclosure provide a shift register unit and a driving method thereof, and a gate driving circuit. The shift register unit includes an input circuit, a next-stage start circuit, a control circuit, a stabilization circuit, and at least one output circuit. The at least one output circuit each can control a voltage of a signal output terminal according to a voltage of a pull-up node, a voltage of a pull-down node, a first voltage signal, a control clock signal from a control clock signal terminal, and a control voltage signal from a control voltage signal terminal. A high level of a second clock signal begins when a high level of a first clock signal ends, and a high level of a third clock signal begins when a high level of the second clock signal ends.


