Shift Register Circuit for OLED PWM Scanning With N-Type TFTs

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Solution Overview

Problem

It is difficult to achieve Pulse Width Modulation (PWM) waveforms in N-type TFTs in OLED displays, particularly in medium to large-sized display devices, due to challenges in internal compensation.

Innovation Solution

A shift register unit is designed with input, control, and output circuits, including transmission and voltage stabilizing circuits, utilizing N-type transistors to control potential levels and generate scanning signals for display driving, enabling PWM waveforms.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If internal compensation is used in OLED displays, then compensation effect is improved and cost is reduced, but PWM waveform generation becomes difficult

Engineering Contradiction:
Improvecompensation effectVSAvoidPWM waveform generation capability
Core Design Contradiction:
ReliabilityVSAdaptability or versatility

Solution Approach 1:

The patent implements dynamic control of transistor gate voltages to generate PWM waveforms. The shift register unit dynamically switches between different voltage levels (ELVDD and ELVSS) through controlled signal transmission, enabling adaptive PWM modulation while maintaining internal compensation functionality.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

The patent changes the voltage parameters at transistor gates through the shift register control mechanism. By varying gate voltages between high and low levels in a controlled sequence, the system generates PWM waveforms while preserving the internal compensation effect, thus resolving the contradiction between compensation reliability and PWM capability.

Inventive Principle:
Principle #35Parameter changes

2Manufacturing precision

If N-type TFTs are used in OLED displays, then manufacturing uniformity is improved, but PWM waveform achievement becomes difficult

Engineering Contradiction:
ImproveuniformityVSAvoidPWM waveform capability
Core Design Contradiction:
Manufacturing precisionVSAdaptability or versatility

Solution Approach 1:

The shift register unit acts as an intermediary control mechanism between the power signal terminal and the transistor gates. It mediates the voltage control by transmitting and transforming signals to achieve PWM waveforms, enabling N-type TFTs to generate PWM while maintaining their manufacturing uniformity advantages.

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The patent segments the control function into multiple transistor stages (first transistor, second transistor, third transistor) within the shift register unit. Each transistor is controlled independently through the signal transmission mechanism, allowing precise PWM waveform generation while leveraging the uniformity of N-type TFTs.

Inventive Principle:
Principle #1Segmentation

3Ease of manufacture

If internal compensation is implemented, then cost is reduced, but computational complexity increases

Engineering Contradiction:
ImprovecostVSAvoidcomputational complexity
Core Design Contradiction:
Ease of manufactureVSDevice complexity

Solution Approach 1:

The shift register unit performs self-service by using its internal transistor network to generate PWM waveforms without requiring external computational control. The internal compensation mechanism automatically regulates the signals through the transistor gates, reducing both cost and computational complexity while maintaining functionality.

Inventive Principle:
Principle #25Self-service

Data Source

PatentUS12505807B2Shift register unit, display driving circuit, display panel and control method
Publication Date: 2025.12.23 HEFEI BOE ZHUOYIN TECH CO LTD
  • US12505807B2 patent drawing
  • US12505807B2 patent drawing
  • US12505807B2 patent drawing

AI summary

A shift register unit, a display driving circuit, a display panel, and a control method. The shift register unit includes: an input circuit configured to provide signals of an input signal terminal (IN) and a power signal terminal (VGH) to first and second pull-up nodes (Q1, Q2); a first control circuit configured to control potentials of the first pull-down node (QB1), and the first pull-up node (Q1); a second control circuit configured to control potentials of the second pull-up node (Q2) and the second pull-down node (QB2) based on the first pull-up node (Q1) and the first pull-down node (QB1); and an output circuit configured to provide the signal of one of the power signal terminal (VGH) and the reference signal terminal (VGL) to an output signal terminal (OUT) under control of the second pull-up node (Q2) and the second pull-down node (QB2).