Shift Register Unit Output Control Module for GOA Circuit Stability
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Solution Overview
Problem
In gate driving circuits, particularly in Gate Driver on Array (GOA) technology, the output waveform often has a falling edge due to gate line load and transistor characteristics, leading to false signal outputs and abnormal displays, especially in high-resolution displays.
Innovation Solution
A shift register unit is designed with an input module, output module, and output control module, where the output control module is connected to the clock signal terminal and signal output terminal, allowing for controlled signal output under the clock signal's control, reducing the falling edge of the waveform and preventing false outputs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GOA technology is used to integrate gate driving circuit into array substrate, then manufacturing cost is reduced and slim bezel design is achieved, but output waveform has falling edge causing false signal output
Solution Approach 1:
The gate driving circuit is divided into multiple independent shift register units (first shift register unit, second shift register unit, etc.), each capable of autonomous operation. This segmentation allows precise control of signal output timing in each unit, eliminating the falling edge issue while maintaining the integrated GOA structure's manufacturing advantages
Solution Approach 2:
The circuit performs preliminary charging of the output control node during the first time period before actual signal output. This preliminary action ensures that when the signal is output in the second time period, the node is already in the correct state, preventing false outputs caused by falling edges
2Device complexity
If gate line load and transistor characteristics are considered in GOA units, then circuit design is simplified, but output waveform develops falling edge
Solution Approach 1:
An output control node is introduced as an intermediary between the input signal and the output signal. This intermediary node allows the circuit to buffer and control the signal transition, eliminating the direct connection that causes falling edges while maintaining overall circuit simplicity
Solution Approach 2:
The circuit operation is divided into distinct periodic phases: a first time period for charging the output control node, and a second time period for outputting the signal. This periodic action ensures clean signal transitions without falling edges by separating the charging and output operations in time
Data Source
AI summary
The present disclosure provides a shift register unit. The shift register unit includes an input module, an output module and an output control module. The input module is connected to an input signal terminal, a first power supply signal terminal and a pull-up node, and is configured to transmit a first power supply signal to the pull-up node. The output module is connected to the pull-up node, a clock signal terminal and an output control node, and is configured to transmit a clock signal to the output control node. The output control module is connected to the output control node, the clock signal terminal and a signal output terminal, and is configured to transmit a signal of the output control node to the signal output terminal under the control of the clock signal.