Shift Register Output Module Stabilizes Signal Levels
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Solution Overview
Problem
The variation in the second clock signal affects the output signal of the shift register due to coupling capacitance, deteriorating the output effect.
Innovation Solution
The shift register design includes an output module with a first and second output unit, and an output control module with a first and second control unit, which stabilize the levels at the nodes to reduce the influence of clock signal variations on the output signal, improving the output effect by controlling signal transmissions between various input and output terminals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the output module uses a simple transistor structure to control signal output, then the device complexity is reduced, but the output signal is affected by coupling capacitance when the clock signal varies, deteriorating the output effect
Solution Approach 1:
The output module is segmented into multiple transistors (M2, M3, M6, M7) with distinct functions: M2 and M3 form the basic output switch, while M6 and M7 are specifically dedicated to compensating for coupling capacitance effects. This segmentation allows the circuit to address the capacitance issue without completely redesigning the output module, maintaining reasonable complexity while improving signal stability.
Solution Approach 2:
Transistors M6 and M7 act as intermediary elements that mediate between the clock signal input and the output signal. These intermediate transistors buffer and stabilize the signal path, isolating the output from the direct influence of clock signal variations and coupling capacitance, thereby improving output reliability without requiring major structural changes.
2Ease of manufacture
If the shift register uses a conventional output control structure, then the ease of manufacture is improved, but the variation of clock signal directly affects the output signal due to coupling capacitance
Solution Approach 1:
The invention changes the electrical parameters of the output control structure by adding parallel transistor paths (M6, M7) that modify the effective capacitance and resistance characteristics. This parameter change reduces the time constant of the RC circuit formed by coupling capacitance and resistance, thereby reducing the influence of clock signal variations on the output signal while maintaining ease of manufacture using standard transistor configurations.
3Device complexity
If the output module uses fewer transistors to reduce device complexity, then the manufacturing cost is reduced, but the output signal quality deteriorates due to coupling capacitance effects
Solution Approach 1:
The output module uses an asymmetric configuration where transistors M2 and M3 have different roles (M2 controls the clock signal path, M3 controls the level signal path), and M6 and M7 are specifically designed with different gate connections to address specific capacitance issues. This asymmetric design allows targeted improvement of output signal quality by addressing the specific coupling capacitance problem without requiring a complete symmetric redesign, achieving better signal quality with minimal additional transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design stabilizes the levels at the nodes, diminishes the impact of clock signal variations on the output signal, and enhances the output effect of the shift register.
Implementation Method 1
an output control module, wherein the output control module comprises a first control unit and a second control unit... the first control unit comprises a fourth TFT, a fifth TFT, a sixth TFT, a seventh TFT, an eighth TFT, a first capacitor and a second capacitor
Data Source
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AI summary
A shift register and a drive method thereof, a gate drive circuit and a display device. The shift register comprises an input module (1), an output module (2) and an output control module (3); the output module (2) comprises a first output unit (21) and a second output unit (22), wherein a first node (P) controls the first output unit (21), the first output unit (21) controls signal transmission between a second clock signal input end (CK2) and a signal output end (OUT-PUT), a second node (Q) controls the second output unit (22), and the second output unit (22) controls signal transmission between a high/low level signal input end (VGH/VGL) and the signal output end (OUT-PUT); the output control module (3) comprises a first control unit (31) and a second control unit (32), wherein the first control unit (31) controls the level of the first node (P), and the second control unit (32) controls the level of the second node (Q). According to the solution of the present disclosure, impact of the change in a clock signal associated with the output module on an output signal can be reduced, thus improving the output effect of the shift register.