Shift Register Circuit for OLED P-Type Transistor Signal Inversion
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Solution Overview
Problem
Existing shift register circuits in display panels, particularly in OLEDs, face challenges in outputting high-level pulse signals using P-type transistors, as the start signal is at a high level, preventing the transistor from turning on, and existing ideas cannot implement the shift function opposite to the turn-on level of P-type transistors.
Innovation Solution
A shift register design comprising an input circuit, first and second control circuits, and an output circuit, which controls the output circuit to produce a signal level opposite to the turn-on level of the transistor, enabling P-type transistors to output high-level signals without threshold loss, and includes sub-circuits like bootstrap and isolation to manage voltage levels effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If P-type transistors are used to output high-level pulse signals, then the transistor structure is simple and manufacturing cost is low, but the start signal being at high level prevents the transistor from turning on
Solution Approach 1:
The patent inverts the conventional approach by making the output signal level opposite to the transistor turn-on level. For P-type transistors that turn on at low levels, the output high-level signal is achieved by outputting a low-level signal through the transistor, which is then inverted to produce the desired high-level output signal.
Solution Approach 2:
The patent introduces bootstrap circuits and isolation circuits as intermediary components. The bootstrap circuit generates intermediate control signals that enable the P-type transistor to properly switch, while the isolation circuit separates different voltage domains to allow the transistor to output high-level signals without direct connection to high voltage sources.
2Ease of operation
If the start signal is at high level, then the signal level matches the desired output level, but the P-type transistor cannot turn on to implement the shift function
Solution Approach 1:
The patent applies inversion by making the transistor output signal level opposite to its turn-on level. The P-type transistor outputs low-level signals when turned on, which are then inverted to produce high-level output signals, thereby achieving both signal level compatibility and proper transistor switching.
Solution Approach 2:
The bootstrap circuit performs preliminary action by pre-charging capacitors and generating appropriate control signals before the main switching operation. This preliminary preparation enables the P-type transistor to properly switch between states and achieve the desired signal output levels.
3Device complexity
If conventional shift register circuits are used, then the structure is simple, but threshold loss occurs when outputting high-level signals
Solution Approach 1:
The isolation circuit acts as an intermediary that separates the transistor switching domain from the high voltage output domain. This allows the P-type transistor to switch at lower voltages without experiencing threshold loss, while still producing accurate high-level output signals through the isolation circuit's voltage translation function.
Solution Approach 2:
The patent inverts the signal level approach to avoid threshold loss. By having the transistor output low-level signals and then inverting them to produce high-level outputs, the transistor operates in its optimal switching range without suffering from threshold voltage drops that would occur when directly outputting high-level signals.
Data Source
AI summary
A shift register and a driving method thereof, a gate driving circuit, and a display device are provided. The shift register includes: an input circuit configured to input an input voltage to a first node under control of a first clock signal; a first control circuit configured to output a first control signal to a first output node under control of the first clock signal, a voltage of the first node, and a second clock signal; a second control circuit configured to output a second control signal to the second output node under control of the voltage of the first node; and an output circuit configured to write a first voltage signal or a second voltage signal into a first output terminal as a first output signal under control of the first control signal and the second control signal.