Shift Register Noise Reduction via Parasitic Capacitor Extraction
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Solution Overview
Problem
Conventional gate monolithic shift registers experience noise in output due to parasitic capacitors, leading to waveform distortion and potential malfunctions, particularly when using amorphous silicon for panel fabrication, which complicates the reduction of voltage requirements and enhances driving capabilities.
Innovation Solution
A shift register design that incorporates a cascade arrangement of stages with a first output transistor having a direct-current voltage applied to its drain, utilizing switched capacitor operations and specific switching elements to prevent feed-through phenomena and reduce noise without increasing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional gate monolithic shift register uses parasitic capacitors for circuit operation, then the circuit can function with standard amorphous silicon fabrication, but noise in output signals and waveform distortion occur
Solution Approach 1:
The patent extracts and removes the parasitic capacitors from the circuit configuration. By eliminating these parasitic elements that cause noise and waveform distortion, the output signal quality is improved without requiring additional complex compensation circuits. The shift register stage operates without the harmful capacitive effects while maintaining functionality.
Solution Approach 2:
The patent converts the potentially harmful effect of parasitic capacitors by designing a circuit that actively compensates for and utilizes these parasitic elements. The circuit configuration transforms the noise-generating parasitic capacitance into a beneficial feature that aids in signal transmission, thereby improving output signal quality while maintaining compatibility with standard amorphous silicon fabrication processes.
2Ease of manufacture
If amorphous silicon is used for panel fabrication to reduce costs, then manufacturing cost decreases, but voltage requirements increase and driving capability is reduced
Solution Approach 1:
The patent changes the electrical parameters of the shift register circuit to optimize performance with amorphous silicon TFTs. By adjusting threshold voltages, operating voltages, and timing parameters, the circuit achieves reliable operation at lower voltages, thereby reducing power consumption while maintaining compatibility with cost-effective amorphous silicon fabrication processes.
3Reliability
If circuit size is increased to reduce noise, then noise reduction capability improves, but device area increases
Solution Approach 1:
The patent merges multiple functions into a single integrated circuit block. By combining the shift register stage, level shifter, and noise reduction mechanisms into one compact unit, the circuit achieves effective noise reduction without proportionally increasing the overall device area. The integrated design allows shared resources and optimized signal paths that reduce total area while maintaining reliability.
Data Source
AI summary
Each stage of a shift register includes: a shift pulse input terminal; a shift pulse output terminal; first to fifth terminals; an input gate, first to fourth switching elements; a first output transistor, and a first circuit, connected between a first output terminal and the second input terminal, which forms a current path between the first output terminal and the second input terminal.