Shift-Register Clock Phase Interpolation for Arbitrary Phase Counts
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Solution Overview
Problem
Existing phase interpolator implementations in integrated circuit devices are limited to representing a number of phases as a power of 2, leading to increased complexity and power consumption as the number of phases increases, due to the requirement for larger phase decoder circuits.
Innovation Solution
The implementation of a phase interpolator circuitry that uses a phase shift register and phase rotation control circuitry to determine shifting directions based on the most significant bits of the phase code, with optional weight decoder and phase-and-weight selection circuitry to derive and assign interpolation weights to clock phases, allowing for interpolation among an arbitrary number of phases.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the number of phases is increased to support arbitrary phase interpolation, then the phase decoder size and complexity increase, but this leads to increased power consumption and device cost
Solution Approach 1:
The phase control code is segmented into two parts: an MSB portion that identifies which two adjacent phases to interpolate, and an LSB portion that determines the relative weights. This segmentation allows the decoder to handle arbitrary numbers of phases without requiring a exponentially larger decoder structure, as each segment handles a specific aspect of the phase selection independently.
Solution Approach 2:
The invention uses a dynamic phase selection mechanism where the MSB portion of the phase control code dynamically selects which pair of adjacent phases to interpolate based on the desired output phase. This dynamic selection approach allows the same decoder structure to adapt to any number of phases without requiring a static, oversized decoder for the maximum possible phase count.
2Adaptability or versatility
If the number of phases is increased to support arbitrary phase interpolation, then the phase decoder size increases, but this also leads to increased power consumption
Solution Approach 1:
By segmenting the phase control code into MSB and LSB portions with distinct functions, the decoder can process phase selection and weight determination separately. This reduces the computational complexity and power consumption compared to a monolithic decoder that would need to handle all phase combinations simultaneously.
Solution Approach 2:
The decoder only processes the necessary portions of the phase control code (MSB for phase pair selection, LSB for weight determination) rather than evaluating all possible phase combinations. This partial action approach reduces power consumption by avoiding unnecessary computational operations while still achieving arbitrary phase interpolation.
3Device complexity
If the number of phases is limited to a power of 2, then the phase decoder size is reduced, but this restricts the ability to perform smooth phase transitions when the phasor wraps around
Solution Approach 1:
The dynamic phase selection based on MSB portions allows the system to smoothly transition between phases by always selecting adjacent phase pairs. When the phasor wraps around from the last phase to the first, the MSB can dynamically switch between phase pairs, ensuring continuous and smooth phase transitions without the restrictions of power-of-2 limitations.
Solution Approach 2:
The phase decoder is designed to be universal and handle any number of phases, not just powers of 2. The MSB-based phase pair selection mechanism works equally well for 4 phases, 6 phases, 8 phases, or any other number, providing smooth transitions in all cases without requiring different decoder architectures.
Data Source
AI summary
An integrated circuit device includes functional circuitry, and serializer/deserializer circuitry for serial communication with the functional circuitry. The serializer/deserializer circuitry includes phase interpolator circuitry for interpolating phases of a clock signal of the integrated circuit device. The phase interpolator circuitry includes a phase shift register having storage locations configured to represent the phases of the clock signal, and phase rotation control circuitry configured to decode a phase code signal to determine a shifting direction for phase selections in storage locations of the phase shift register. The phase rotation control circuitry may be configured to determine the shifting direction based on only the most significant bit and the second most significant bit of the phase code signal. The phase interpolator circuitry may further include weight decoder circuitry configured to derive, from the phase code signal, interpolation weights to control combination of selected phases of the clock signal.