Shift Register Unit Phase-Inverted Signal Output
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Solution Overview
Problem
In display technology, existing shift register units for GOA (Gate driver On Array) circuits face challenges in efficiently driving TFTs, leading to issues like residual images, crosstalk, and threshold voltage shifts due to shared high-level and low-level signals, which affect both the display area and the GOA region, and are limited by driving voltage amplitude.
Innovation Solution
A shift register unit design that outputs phase-inverted signals to drive double-gate TFTs, reducing driving voltage and enhancing driving ability, while compensating for ON/OFF current drift and threshold voltage shifts without impacting GOA region TFTs, by using a first and second circuit unit with specific transistor configurations and voltage control.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If shared high-level and low-level signals are used to drive TFTs, then circuit complexity is reduced, but display quality deteriorates due to residual images, crosstalk, and threshold voltage shifts
Solution Approach 1:
The patent divides the gate drive circuit into separate high-level signal path and low-level signal path, with independent timing control for each. This segmentation allows different timing adjustments for pull-up and pull-down operations, preventing the overlapping signals that cause residual images and crosstalk while maintaining manageable circuit complexity through modular design.
Solution Approach 2:
The patent introduces dynamic timing control mechanisms where the timing of high-level and low-level signals can be independently adjusted based on operational requirements. This dynamic adjustment capability enables optimization of signal timing to prevent threshold voltage shifts and improve display quality without requiring a completely redesigned static circuit architecture.
2Productivity
If conventional shift register units are used, then GOA region TFTs are driven, but display area TFTs suffer from threshold voltage shifts and current drift
Solution Approach 1:
The patent applies different timing control strategies to different operational phases: during normal operation, standard timing is applied; during compensation phases, adjusted timing is applied specifically to correct threshold voltage shifts and current drift in display area TFTs. This local quality approach allows targeted correction without affecting the overall driving capability of the GOA circuit.
Solution Approach 2:
The patent incorporates feedback mechanisms that monitor the state of display area TFTs and adjust signal timing accordingly. This feedback loop detects threshold voltage shifts and current drift, then modifies the timing of gate signals to compensate for these changes, maintaining TFT stability while preserving the productivity benefits of the GOA architecture.
3Reliability
If phase-inverted signals are output, then logic power consumption is reduced and TFT reliability is improved, but circuit complexity increases
Solution Approach 1:
The patent combines the phase-inversion function with existing timing control circuits in the shift register unit. By merging the phase-inversion logic into the timing control structure rather than adding separate inversion circuits, the patent reduces power consumption and improves TFT reliability while minimizing the increase in circuit complexity through integrated design.
Data Source
Figure 1A~1B
Figure 2~3
Figure 4A~4B
AI summary
A shift register unit, a driving device, a display device and a driving method are disclosed. The shift register unit (10) includes a first circuit unit (100) and a second circuit unit (200); the first circuit unit (100) includes an input terminal (INPUT), a reset terminal (RESET), a clock signal terminal (CLK), a first voltage terminal (VGH), a second voltage terminal (VGL) and a first output terminal (OUTPUT), and is configured to output a first output signal of the shift register unit (10) from the first output terminal (OUTPUT); the second circuit unit includes a third voltage terminal (VGH2), a fourth voltage terminal (VGL2) and a second output terminal (OUTPUT2), and is configured to output a second output signal of the shift register unit (10) from the second output terminal (OUTPUT2), at least under the control of the first output signal; and the second output signal and the first output signal are mutually phase-inverted signals.