Shift Register Pin Reduction for Mini LED Display
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Solution Overview
Problem
Conventional Mini LED driving circuits require a large number of pins and occupy significant space due to the need for multiplexing and channel pins, leading to increased complexity and reduced display quality.
Innovation Solution
A first shift register design that includes multiple units connected in a specific configuration to reduce the number of driving pins and wiring space, allowing for independent connection with gate lines and improved local dimming functionality, while maintaining signal integrity through denoising modules.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If conventional Mini LED driving circuits use multiplexing and channel pins, then the driving function is achieved, but the number of pins and occupied space increases significantly
Solution Approach 1:
The shift register is divided into multiple units (first unit, M second units, and N third units) with different connection configurations. Each unit independently drives specific gate lines, segmenting the driving function to reduce the number of pins required at the driver IC while maintaining comprehensive coverage of all gate lines.
Solution Approach 2:
The patent introduces a multi-dimensional connection structure where units are arranged in sequences and connected through multiple pathways (first signal output terminal, second signal output terminal, third signal output terminal). This dimensional expansion allows signal distribution to multiple gate lines through fewer input pins, effectively reducing pin count while maintaining signal integrity.
2Device complexity
If the number of driving pins is reduced, then wiring space is simplified, but signal integrity and stability may be compromised
Solution Approach 1:
Different units are configured with different connection qualities and characteristics. The first unit connects to M second units through first signal output terminals, while second units connect to N/M third units through second signal output terminals. Each unit's local connection structure is optimized for its specific function, ensuring signal stability while reducing overall wiring complexity.
Solution Approach 2:
The shift register units act as intermediaries between the driver IC and gate lines. By introducing multiple intermediate units with specific connection configurations, the patent enables signal distribution to multiple gate lines through fewer direct connections from the driver IC, maintaining signal integrity while reducing wiring space.
3Manufacturing precision
If more pins are used for high-resolution local dimming, then display quality improves, but the driver IC complexity and space increase
Solution Approach 1:
The shift register units serve multiple functions simultaneously. Each unit can drive multiple gate lines through different output terminals, and different units can be configured to drive different numbers of gate lines based on local requirements. This multi-functionality enables high-resolution local dimming without proportionally increasing driver IC complexity.
Solution Approach 2:
The connection configuration between units is dynamically optimized for different driving scenarios. The first unit can drive M second units, which in turn drive N/M third units, creating a dynamic signal distribution network that adapts to the specific requirements of high-resolution local dimming while maintaining manageable driver IC complexity.
Data Source
AI summary
Disclosed are a first shift register, a driving method for the same, a gate driving circuit and a display device. The first shift register includes a first unit, M second units and N third units. A first signal output terminal of the first unit is connected with M second signal input terminals of the M second units. A second signal output terminal of each second unit is connected with third signal input terminals of N/M third units respectively. The first unit outputs a voltage of a first clock signal terminal to the first signal output terminal and a fourth signal output terminal under the control of a first signal input terminal and a second clock signal terminal and outputs a voltage of a first voltage terminal to the first signal output terminal and the fourth signal output terminal.