Shift Register Circuit Positive Feedback Node Reset

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Solution Overview

Problem

The response speed of shift register circuits in display devices is adversely affected due to the use of a signal from the output end as feedback to trigger pull-up or pull-down actions, leading to increased response time and power consumption.

Innovation Solution

A shift register circuit design incorporating a positive feedback unit that rapidly resets internal nodes, allowing the positive feedback unit to trigger pull-up or pull-down actions instead of relying on output-end feedback, thereby reducing response time and power consumption.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a signal from the output end is used as feedback to trigger pull-up or pull-down actions, then the shift register circuit can maintain stable operation, but the response time increases and response speed decreases

Engineering Contradiction:
Improvestable operationVSAvoidresponse time
Core Design Contradiction:
ReliabilityVSLoss of time

Solution Approach 1:

The patent inverts the conventional feedback approach by using a positive feedback unit that triggers pull-up or pull-down actions based on the opposite state of the output signal. Instead of waiting for the output signal to indicate the next state, the circuit proactively switches internal nodes to the opposite state, thereby reducing response time while maintaining operational stability through the feedback mechanism.

Inventive Principle:
Principle #13The other way round (Inversion)

2Reliability

If a signal from the output end is used as feedback to trigger pull-up or pull-down actions, then the shift register circuit can maintain stable operation, but power consumption increases

Engineering Contradiction:
Improvestable operationVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSLoss of energy

Solution Approach 1:

The positive feedback unit performs preliminary actions by proactively switching internal nodes to the opposite state before the output signal actually changes. This anticipatory switching reduces the duration of high-power states and minimizes energy consumption while maintaining stable operation through the feedback control mechanism.

Inventive Principle:
Principle #10Preliminary action

3Productivity

If the positive feedback unit triggers pull-up or pull-down actions based on opposite state, then response speed increases and power consumption decreases, but the circuit structure becomes more complex

Engineering Contradiction:
Improveresponse speedVSAvoidcircuit structure
Core Design Contradiction:
ProductivityVSDevice complexity

Solution Approach 1:

The patent merges the positive feedback unit with the existing switch units and internal nodes of the shift register circuit. By integrating these functions into a unified structure rather than adding completely separate components, the circuit achieves improved response speed and reduced power consumption while minimizing the increase in structural complexity.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9881556B2Shift register circuit, its driving method, array substrate and display device
Publication Date: 2018.01.30 BOE TECHNOLOGY GROUP CO LTD
  • US9881556B2 patent drawing
  • US9881556B2 patent drawing
  • US9881556B2 patent drawing

AI summary

The present disclosure provides a shift register circuit, which includes a first switch unit connecting an input end to a first node when a positive-phase clock signal is at a first level; a second switch unit applying a negative-phase clock signal to an output end when the first node is at the first level; a positive feedback unit enabling the second node to be at a second level when the first node is at the first level and enabling the first node to be at the second level when the second node is at the first level; a third switch unit enabling a third node to be at the first level when the positive-phase clock signal is at the first level; a fourth switch unit connecting the second node to the third node when the negative-phase clock signal is at the first level; and a fifth switch unit.