Shift Register Power-Off Control Circuit for Display Panel
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Solution Overview
Problem
Display abnormalities occur in gate driving circuits due to the need for all signal terminals to be at an active level during power-off, leading to undesired outputs when powered on again.
Innovation Solution
The proposed shift register design includes a second control circuit that allows for independent control of the output signal terminal's potential during power-off, using a pull-down and pull-up mechanism without requiring all signal terminals to be at an active level, and includes a noise reduction circuit to stabilize the pull-down node's potential.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If all signal terminals are set to active level during power-off, then the gate driving circuit can be properly initialized, but display abnormalities occur due to undesired outputs when powered on again
Solution Approach 1:
The patent segments the control of signal terminals into two independent groups: first control circuits that set pull-up nodes to active level, and second control circuits that set pull-down nodes to inactive level. This segmentation allows different terminals to be controlled independently during power-off, preventing undesired outputs while ensuring proper initialization.
Solution Approach 2:
The patent inverts the traditional power-off control approach by separately controlling pull-up and pull-down nodes. Instead of setting all terminals to active level simultaneously, the pull-down nodes are set to inactive level while pull-up nodes are set to active level, reversing the conventional wisdom and preventing display abnormalities.
2Object-generated harmful factors
If pull-up node is set to inactive level during power-off, then undesired outputs are prevented, but noise effects may interfere with proper initialization
Solution Approach 1:
The patent introduces a noise reduction circuit as an intermediary between the second control circuit and the pull-down node. This circuit includes a capacitor that filters noise and stabilizes the pull-down node potential, preventing noise effects from interfering with proper initialization while maintaining the inactive level during power-off.
Solution Approach 2:
The noise reduction circuit prepares for potential noise interference by incorporating a capacitor that can absorb and filter noise before it affects the pull-down node. This beforehand cushioning ensures that even if noise is present during power-off, it cannot interfere with the initialization process.
3Adaptability or versatility
If second control circuit is added to independently control output signal terminal, then power-off control is improved, but device complexity increases
Solution Approach 1:
The second control circuit is designed with multi-functionality, serving both as a control circuit for the output signal terminal and as part of the overall power-off control system. The circuit uses standard transistor components that can be integrated into existing gate driving circuit architectures, reducing the actual complexity increase while maintaining enhanced power-off control flexibility.
Data Source
AI summary
The present disclosure provides a shift register, a gate driving circuit, a display panel, and a driving method thereof. The shift register includes: an input circuit; an output circuit; a first control circuit configured to provide a potential of a first control signal terminal to a pull-down node, and provide a potential of a reference signal terminal to the pull-down node according to the potential of the pull-up node; and a second control circuit connected to the pull-down node, a second control signal terminal, the output signal terminal, and the reference signal terminal, wherein the second control circuit is configured to pull down a potential of the output signal terminal during a display phase under the control of a potential of the pull-down node and a potential of the second control signal terminal, and pull up the potential of the output signal terminal in a power-off phase.