Shift Register Power Consumption Reduction via Sub-Circuit Segmentation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Existing gate driving circuits for displays have high power consumption due to large capacitance on clock signal lines, which is proportional to the frequency and capacitance of the clock signal line, leading to significant dynamic power consumption.
Innovation Solution
A shift register design with a power consumption-reducing sub-circuit and an output sub-circuit, where the power consumption-reducing sub-circuit is connected to the clock signal terminal and control terminal, and outputs a signal to the output sub-circuit, reducing the size of transistors in the power consumption-reducing sub-circuit and thus the gate-source capacitance, resulting in lower capacitance on the clock signal line and reduced dynamic power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If the gate driving circuit uses a conventional design with direct clock signal connection to output transistor, then the circuit structure is simple, but the capacitance on clock signal line is large leading to high power consumption
Solution Approach 1:
The patent divides the gate driving circuit into distinct functional sub-circuits: a power consumption-reducing sub-circuit and an output sub-circuit. The power consumption-reducing sub-circuit includes transistors specifically designed to minimize capacitance on the clock signal line, while the output sub-circuit handles the actual signal output. This segmentation allows optimization of power consumption in the clock path without compromising output functionality.
Solution Approach 2:
The patent introduces an intermediate power consumption-reducing sub-circuit between the clock signal input and the output transistor. This intermediary circuit acts as a buffer that reduces the capacitive load on the clock signal line while maintaining proper signal transmission to the output, thereby reducing power consumption without eliminating the need for adequate signal drive capability.
2Speed
If the transistor size is increased to reduce signal delay, then the signal transmission speed improves, but the gate-source capacitance increases leading to higher power consumption
Solution Approach 1:
The patent applies different transistor sizing strategies to different parts of the circuit. In the power consumption-reducing sub-circuit, transistors are sized to minimize capacitance on the clock signal line. In the output sub-circuit, transistors can be sized appropriately for signal drive capability. This local differentiation allows optimization of both power consumption and signal speed in their respective domains without the trade-off that would exist in a uniformly sized circuit.
Solution Approach 2:
The patent enables dynamic control of transistor operation through the differentiated circuit architecture. The power consumption-reducing sub-circuit can dynamically manage the clock signal transmission with minimal capacitive effect, while the output sub-circuit dynamically responds to signal requirements. This dynamic operation allows the circuit to achieve fast signal transmission when needed while maintaining low power consumption during clock signal phases.
Data Source
AI summary
Embodiments of the present disclosure provide a shift register, a gate driving circuit, and a display apparatus. The shift register comprises a power consumption-reducing sub-circuit and an output sub-circuit; wherein: the power consumption-reducing sub-circuit is connected to a clock signal terminal, a control terminal, and the output sub-circuit, the power consumption-reducing sub-circuit is used to output a signal of the clock signal terminal to the output sub-circuit under the control of the control terminal; the output sub-circuit is connected to the clock signal terminal through the power consumption-reducing sub-circuit and is also connected to an output terminal and a pull-up node, the output sub-circuit is used to output an output signal of the power consumption-reducing sub-circuit to the output terminal under the control of the pull-up node.