Shift Register Power Saving for Image Sensor Readout
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Image sensors face increased power consumption and signal noise due to higher resolution demands, particularly as the frequency of read and address clocks overlap with data transmission timing, leading to inefficiencies in power conservation and noise reduction.
Innovation Solution
Implementing a logic combination of AND gates and OR gates for local and global buffer control to manage data transmission, disabling shift registers after data transfer and using delayed clock signals to reduce overlap between counter timing and data transmission, thereby reducing power consumption and signal noise.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the frequency of read clock and address clock is increased, then data transmission speed is improved, but power consumption increases
Solution Approach 1:
The patent applies periodic action by enabling shift registers and buffers only during specific time periods when data transmission is required, and disabling them during other periods. This periodic enablement based on timing signals allows high-speed transmission when needed while conserving power during idle periods, directly resolving the contradiction between transmission speed and power consumption.
2Speed
If the frequency of read clock and address clock is increased, then data transmission speed is improved, but signal noise increases
Solution Approach 1:
The patent introduces timing signals as intermediary control elements that mediate between the clock signals and the shift registers/buffers. These timing signals coordinate the operation of multiple shift registers and buffers, ensuring that data transmission occurs in a controlled sequence that avoids overlapping operations and reduces signal noise, while still maintaining high transmission speeds.
3Reliability
If shift register operation is continuous, then data transmission reliability is improved, but power consumption increases
Solution Approach 1:
The patent applies dynamics by making the shift registers and buffers dynamically controllable through timing signals. Instead of continuous operation, the shift registers are enabled only when needed for data transmission and disabled otherwise. This dynamic control maintains data transmission reliability during active periods while significantly reducing power consumption during idle periods.
4Device complexity
If counter timing overlaps with data transmission timing, then device complexity is reduced, but signal noise increases
Solution Approach 1:
The patent applies preliminary action by using timing signals to pre-coordinate the operation of counters and shift registers before data transmission begins. The timing signals ensure that counter operations and data transmission are properly sequenced and do not overlap, preventing signal noise while maintaining relatively simple device architecture through systematic timing control.
Data Source
AI summary
A data transmission circuit of an image sensor. In one embodiment, the data transmission circuit includes a plurality of banks coupled in a series. A peripheral bank of the plurality of transmission banks is coupled to a function logic. Each bank includes a plurality of local buffers coupled to a local buffer control and a plurality of global buffers coupled to a global buffer control. The local buffers are settable to their enabled or disabled state by a bank enable command at the local buffer control. The enabled local buffers are configured to transfer local data to shift registers of their respective bank. The disabled local buffers are configured not to transfer the local data to the shift register of their respective bank.