Shift Register Voltage Stress Reduction via Pre-Charge Clocking
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Solution Overview
Problem
Conventional shift registers used in liquid crystal displays face issues with voltage stress, leading to uneven display and reduced transistor life due to prolonged high voltage application, which limits charge time and degrades display quality.
Innovation Solution
A shift register design with cascaded register units, utilizing a pull-up and pull-down circuit configuration driven by specific clock signals and a driving signal, allowing for pre-charging and reducing the time high voltage is applied, along with a phase difference between clock signals to manage voltage transitions efficiently.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the gate driver outputs scanning signal at fixed interval, then the display timing is controlled, but the charge time period is limited and display quality degrades
Solution Approach 1:
The invention applies preliminary action by introducing a pre-charge phase before the main scanning operation. The gate driver outputs a pre-charge signal that charges the pixel capacitors in advance, extending the effective charge time period. This preliminary charging action occurs before the main data writing phase, allowing pixels to be fully charged without compromising the fixed scanning interval, thereby improving display quality while maintaining productivity.
2Duration of action of stationary object
If high voltage level is applied at gate of transistor for long time, then the shift register operates continuously, but voltage stress phenomenon causes threshold voltage shift and reduces transistor life
Solution Approach 1:
The invention applies periodic action by implementing a dual-phase clock signal system (CLK and CLK_B) that periodically switches between charge and discharge states. The gate voltage is applied in periodic pulses rather than continuously, with each cycle including a pre-charge phase followed by a main operation phase. This periodic gating reduces the cumulative voltage stress on transistors while maintaining continuous operational capability of the shift register, thereby extending transistor life without sacrificing operational duration.
3Reliability
If the output signal of next stage register unit is used to control current stage, then voltage stress is reduced, but signal interference occurs
Solution Approach 1:
The invention introduces an intermediary mechanism by using a clock signal generator that produces differentiated clock signals (CLK and CLK_B) with specific phase relationships. Instead of directly using the next stage output to control the current stage, the system employs these intermediary clock signals to coordinate the operation of pull-up and pull-down circuits. This intermediary clocking scheme reduces voltage stress through controlled timing while avoiding signal interference by maintaining proper signal isolation and timing relationships.
Data Source
AI summary
A shift register includes a plurality of register units cascade-connected with each other. Each register unit includes a pull-up circuit, a pull-up driving circuit, a pull-down circuit, and a pull-down driving circuit. The pull-up circuit coupled to a first clock signal is used for providing an output signal. The pull-up driving circuit turns on in response to a driving pulse from a previous register unit and a second clock signal, and turns off in response to a third clock signal. The pull-down driving circuit which is coupled to an input node of the pull-down circuit, turns on in response to a first clock signal, and turns off in response to a the first clock signal or output of the pull-up driving circuit.