Shift Register Group Pull-Down Speed for Display Panels
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Solution Overview
Problem
Conventional gate driver technologies struggle to quickly pull down output signals for scan lines in display panels, leading to potential image abnormalities due to delayed signal disablement, especially at higher image frame rates.
Innovation Solution
A shift register group with series-coupled shift registers and a driving method that includes control circuits to manage clock signals and driving node voltages, enabling faster pull-down of output signals by controlling the transmission of control signals and voltages across the shift register stages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the output signal is kept enabled for a longer period to ensure complete scanning of the scan line, then the scanning completeness is improved, but the image quality deteriorates due to signal overlap with the next frame
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitive load through the third control signal before the main output signal is disabled. This preparatory charging action ensures that when the output signal is pulled down, the capacitive load is already in a state that facilitates rapid discharge, thereby enabling fast signal transition without compromising scanning completeness or image quality
Solution Approach 2:
The patent introduces a third control signal as an intermediary mechanism that mediates between the output signal and the capacitive load. This intermediary signal independently controls the charging state of the capacitive load, allowing the output signal to be disabled quickly while maintaining proper signal levels through the mediated action of the third control signal
2Manufacturing precision
If the output signal is pulled down quickly to prevent image abnormalities, then the image quality is improved, but the scanning completeness may be compromised
Solution Approach 1:
The third control signal performs preliminary charging of the capacitive load before the output signal is pulled down. This ensures that when the output signal is quickly disabled, the capacitive load is already prepared to maintain proper voltage levels, preventing image abnormalities while ensuring scanning completeness
Solution Approach 2:
The patent employs periodic action through the coordinated timing of multiple control signals (first, second, and third control signals) that operate in periodic cycles. The third control signal periodically charges the capacitive load in synchronization with the output signal transitions, enabling rapid pull-down while maintaining scanning integrity through rhythmic, coordinated signal operations
3Manufacturing precision
If the enable period of the output signal is shortened to match higher frame rates, then the image quality is improved, but the pull-down speed requirement increases
Solution Approach 1:
The third control signal performs preliminary charging of the capacitive load before the output signal needs to be pulled down. This preliminary action reduces the time required for the pull-down operation by ensuring the capacitive load is already in a favorable state, thereby meeting the increased pull-down speed requirements of higher frame rates
Solution Approach 2:
The patent applies parameter changes by dynamically controlling the voltage state of the capacitive load through the third control signal. By changing the charging parameter of the capacitive load in advance, the system achieves faster pull-down speed while maintaining the shortened enable period required for high frame rate operation
Data Source
AI summary
A shift register group includes a plurality of series-coupled shift registers each being configured to provide an output signal. The third control signal of a first sift register of the plurality of shift registers is the output signal provided by the shift register N stages after the first shift register, and the fourth control signal of the first sift register is the voltage at the driving node of the shift register 2N stages after the first shift register, wherein N is a natural number. A driving method of the aforementioned shift register group is also provided.