Shift Register Pull-Down Circuit Threshold Voltage Shift
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Solution Overview
Problem
In Gate Driver on Array (GOA) technology, the gate of a transistor in the pull-down sub-circuit is influenced by a high level bias voltage for a long time, causing a shift in the threshold voltage and affecting the performance of the display panel, leading to noise issues and reduced stability and reliability.
Innovation Solution
A shift register is designed with a pull-down sub-circuit controlled by mutually inverted third and fourth clock signal terminals, whose signal periods are half of the first or second clock signal terminal periods, reducing the time transistors are influenced by high level bias voltage and maintaining low levels at the pull-up node and signal output terminal.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the gate of the transistor in the pull-down sub-circuit is influenced by high level bias voltage for a long time, then the transistor can maintain its switching function, but the threshold voltage of the transistor shifts, affecting the performance and reliability of the display panel
Solution Approach 1:
The patent introduces a periodic control mechanism where the pull-down sub-circuit is activated only during specific clock phases (CLKC and CLKD) rather than continuously. The control transistors (T11, T12, T15, T16) are periodically switched on and off based on clock signals, creating a periodic action that limits the duration of high level bias voltage influence on the gate, thereby preventing threshold voltage shift while maintaining the necessary pull-down function during active periods
Solution Approach 2:
The patent transforms the static pull-down sub-circuit into a dynamic one by introducing time-varying control signals. The control transistors are dynamically switched based on clock phases, making the pull-down function active only when needed. This dynamic control allows the circuit to adapt its behavior over time, enabling the gate to be influenced by high level bias voltage only during specific periods rather than continuously, thus resolving the threshold voltage shift issue
2Object-affected harmful factors
If the pull-down sub-circuit is continuously active to maintain low level at the pull-up node, then the noise is suppressed, but the transistor threshold voltage shifts due to prolonged high level bias voltage influence
Solution Approach 1:
The patent implements periodic activation of the pull-down sub-circuit through clock-controlled transistors T11, T12, T15, and T16. These transistors are switched on during specific clock phases (CLKC and CLKD) and off during other phases, creating a periodic pull-down action that suppresses noise during active periods while allowing the gate to rest during inactive periods, thereby preventing cumulative threshold voltage shift
Solution Approach 2:
The patent uses the reset sub-circuit to preliminarily set the pull-up node to a known low level state before the shift register operation begins. The reset transistors (T3, T4) are activated during the reset phase to ensure the pull-up node starts at a stable low level, preventing noise issues during initialization while avoiding prolonged high level bias voltage influence that would cause threshold voltage shift
Data Source
AI summary
The embodiments of the present disclosure provide a shift register, a method for driving the same, and a gate driving circuit. A pull-down sub-circuit of the shift register is under the control of a third clock signal terminal and a fourth clock signal terminal, wherein signals of the third clock signal terminal and the fourth clock signal terminal are mutually inverted signals, and signal periods of the third clock signal terminal and the fourth clock signal terminal are a half of a signal period of a first clock signal terminal or a second clock signal terminal.