Shift Register Circuit Pull-Down Control for LCD Display

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Solution Overview

Problem

The existing gate driving circuits in flat LCD displays, particularly those using Gate On Array technology, face issues with the pull-down speed of gate control signals affecting the driving effect on pixel arrays, leading to misoperation of switches and abnormal image display due to frequency signal coupling in shift registers.

Innovation Solution

A shift register circuit design incorporating a pull-down control circuit and capacitors to manage the voltage level of nodes, eliminating interference signals by controlling the operation status of switches, thereby ensuring proper signal transmission and preventing abnormal image display.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Ease of manufacture

If Gate On Array technology is used to integrate the gate driving circuit directly on the array substrate, then the production cost is reduced and the panel thickness is decreased, but the pull-down speed of the gate control signal deteriorates, causing switch misoperation and abnormal image display

Engineering Contradiction:
Improveproduction costVSAvoidswitch operation accuracy
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The shift register circuit is divided into multiple stages, with each stage independently controlling a segment of the pixel array. This segmentation allows for optimized signal propagation and pull-down control in each stage, preventing signal interference and switch misoperation while maintaining the GOA integration benefits

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

A carefully designed node structure acts as an intermediary between the frequency signal input and the gate control signal output. This intermediate node configuration isolates the periodic frequency signal from directly coupling to subsequent stages, preventing misoperation while maintaining signal transmission efficiency

Inventive Principle:
Principle #24Intermediary (Mediator)

2Productivity

If the frequency signal is coupled to the shift register, then the shift register can operate, but the periodic frequency signal causes multiple switches to misoperate during turning on and off, displaying abnormal images

Engineering Contradiction:
Improvesignal transmission speedVSAvoidinterference signal
Core Design Contradiction:
ProductivityVSObject-affected harmful factors

Solution Approach 1:

The harmful periodic coupling effect is extracted and isolated from the main signal path by designing specific node connections. The frequency signal is introduced at controlled points where it can be converted to proper control signals without causing harmful periodic interference to subsequent stages

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The circuit is designed with preliminary pull-down paths that are activated before the frequency signal can cause harmful coupling. This preliminary action ensures that nodes are properly discharged and switches are in the correct state before new signals arrive, preventing misoperation

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS11004416B2Shift register circuit and display panel using the same
Publication Date: 2021.05.11 HKC CORP LTD
  • US11004416B2 patent drawing
  • US11004416B2 patent drawing
  • US11004416B2 patent drawing

AI summary

A shift register comprises: a first switch electrically coupled to a control signal, and to a first node; a second switch electrically coupled to the first node, to a frequency signal, and to a first output signal; a third switch electrically coupled to a second output signal, to the first output signal, and to a low predetermined voltage level; a fourth switch electrically coupled to a second node, to the first node, and to the low predetermined voltage level; a fifth switch electrically coupled to the first node, to the frequency signal, and to a third node; and a pull-down control circuit electrically coupled to the frequency signal, the low predetermined voltage level and the second node.