Shift Register Pull-Down Circuit Merging for LCD Panel Reliability
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Solution Overview
Problem
The reliability of shift registers in LCD panels is compromised due to the deterioration of amorphous silicon (a-Si) and low temperature polycrystalline silicon (LTPS) thin film transistors (TFTs) when subjected to high-frequency clock signals, leading to stress and reduced performance over time.
Innovation Solution
A shift register design where each pair of stages shares a single pull-down control circuit, utilizing a series of transistors and capacitors to manage clock signals and reduce stress on TFTs, thereby simplifying the Gate-on-Array (GOA) architecture and enhancing reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple pull-down circuit sets are applied to reduce stress on TFTs, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges the pull-down control circuits by sharing them between adjacent shift register stages. Specifically, the pull-down control circuit of stage n is shared with both stage n-1 and stage n+1, reducing the total number of separate pull-down control circuits from N to approximately N/2. This merging approach maintains the stress-reduction function while significantly lowering device complexity.
Solution Approach 2:
The shared pull-down control circuit performs multiple functions: it controls the pull-down operation for its own stage while also serving as the pull-down control circuit for adjacent stages. This multi-functionality allows a single circuit to reduce stress for multiple TFTs, achieving reliability improvement without proportional increase in complexity.
2Productivity
If high-frequency clock signals are used to generate sequentially shifted output signals, then productivity is improved, but reliability deteriorates due to TFT stress
Solution Approach 1:
The pull-down control circuit acts as an intermediary mechanism that mediates between the high-frequency clock signals and the TFTs. It selectively activates pull-down operations only when necessary, protecting TFTs from continuous high-frequency stress while still enabling the shift register to operate at high frequencies for improved productivity.
Solution Approach 2:
The pull-down control circuit implements periodic action by activating pull-down operations only during specific time intervals rather than continuously. This periodic activation pattern allows the shift register to maintain high-frequency operation for productivity while giving TFTs periodic relief from stress, thereby maintaining reliability.
Data Source
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AI summary
A shift register comprises a plurality of stages, {Sn}, n = 1, 2, ..., N, N being a positive integer. In one embodiment, each stage Sn includes a pull-up circuit having an input for receiving one of a first clock signal, CK1, and a second clock signal, XCK1, an output for responsively outputting an output signal, On, and an input node Qn, a pull-up control circuit electrically coupled to the input node Qn and configured such that when receiving a first input signal, the pull-up control circuit responsively generates a signal that is provided to the input node Qn to turn on the pull-up circuit, a pull-down circuit electrically coupled to the input node Qn and configured to provide a first voltage to one of the input node Qn and the output of the pull-up circuit, and a pull-down control circuit configured to receive one of a third clock signal, CK2, and a fourth clock signal, XCK2, and responsively generate the first voltage to turn on the pull-down circuit of the stage Sn and the pull-down circuit of one of the stage Sn-1 and the stage Sn+1.