Shift Register Unit Pull-Down Control Node Noise Reduction
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Solution Overview
Problem
In the pull-down holding phase of a display period, the potential of the pull-down control node cannot remain at a low level, leading to electric leakage and noise in the gate drive signal and pull-up node in TFT-LCD displays.
Innovation Solution
A shift register unit with a pull-down control node control unit that manages the connection of the pull-down node to either the first or second clock signal input terminal based on the phase of the clock signals, using transistors to control the potential of the pull-down control node and prevent electric leakage, thereby ensuring a low level is maintained during the pull-down holding phase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the pull-down control node PD_CN is not turned off well during the pull-down holding phase, then the potential of the pull-down node PD can be pulled down by the second clock signal CLK, but this causes large noises at the pull-up node PU and gate drive signal output terminal
Solution Approach 1:
The patent introduces a pull-down control node control unit with control transistors (M141, M142, M143) that act as intermediaries to precisely control the potential of the pull-down control node PD_CN. These control transistors mediate between the clock signals and the pull-down control node, ensuring that PD_CN remains at the correct potential level during the pull-down holding phase, thereby preventing noise while maintaining proper signal control.
Solution Approach 2:
The patent changes the control parameter of the pull-down control node PD_CN by using multiple clock signals (CLKB, CLK) with opposite phases to dynamically adjust the potential of PD_CN. By changing the phase relationship and timing of clock signals controlling the pull-down transistors, the patent ensures that PD_CN remains at a low level during the pull-down holding phase, preventing noise generation while maintaining reliable signal operation.
2Reliability
If the pull-down control node PD_CN remains at a high level during the pull-down holding phase, then the pull-down node PD switches to the first clock signal CLKB and maintains high potential, but this causes erroneous output at the gate drive signal output terminal
Solution Approach 1:
The patent segments the control of the pull-down control node PD_CN into multiple independent control transistors (M141, M142, M143), each controlled by different clock signals. This segmentation allows precise control of PD_CN potential at different phases, ensuring it remains at the correct level during the pull-down holding phase to prevent erroneous output, while distributing the control complexity across multiple simple transistor switches rather than a single complex control mechanism.
Solution Approach 2:
The patent uses periodic clock signals CLKB and CLK with opposite phases to periodically control the pull-down transistors and maintain PD_CN at the correct potential during the pull-down holding phase. This periodic action synchronized with the display period ensures that PD_CN remains at a low level at the right time, preventing erroneous output while using simple periodic switching rather than complex continuous control.
Data Source
AI summary
The shift register unit comprises: a gate drive signal output terminal, a first clock signal input terminal, a second clock signal input terminal, a low level input terminal, a pull-up control unit, a pull-down unit, a pull-down node control unit and a pull-down control node control unit. In a pull-down holding phase of a display period, a first clock signal input through the first clock signal input terminal and a second clock signal input through the second clock signal input terminal have opposite phases. When the first clock signal has a high level, the pull-down control node control unit controls the pull-down control node to be connected to the first clock signal input terminal. When the second clock signal has a high level, the pull-down control node control unit controls the pull-down control node to be connected to the low level input terminal.