Shift Register Pull-Up Node Bootstrap Function
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Solution Overview
Problem
In N-type bidirectional scanning GOA circuits, the bootstrap function of the capacitor at the pull-up node is often invalid, leading to abnormal gate driving signals due to insufficient potential at the pull-up node, affecting the reliability and operation of display panels.
Innovation Solution
A shift register design with a pull-up node control circuit, a capacitor, a pull-down node control circuit, and an output circuit that ensures the potential of the pull-up node is maintained high through specific input and clock signals, ensuring the output transistor is fully turned on and the gate driving signal is output normally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If one terminal of the capacitor is coupled to a low potential terminal, then the circuit structure is simple, but the bootstrap function of the capacitor becomes invalid and the potential of the pull-up node cannot be maintained high
Solution Approach 1:
Instead of coupling one terminal of the capacitor to a low potential terminal (conventional approach), the patent inverts the connection by coupling it to the pull-up node. This inversion enables the capacitor to perform its bootstrap function effectively, maintaining the potential of the pull-up node high during the output period and ensuring the output transistor remains fully turned on.
2Ease of operation
If the potential of the pull-up node is not maintained high, then the circuit operation is simpler, but the output transistor cannot be fully turned on causing abnormal gate driving signal output
Solution Approach 1:
The patent applies preliminary action by pre-charging the capacitor during the input period before the output phase. This preliminary charging action ensures that when the output period begins, the capacitor is already charged and ready to perform the bootstrap function, maintaining the pull-up node potential high and ensuring the output transistor is fully turned on without requiring complex real-time control.
3Device complexity
If the capacitor bootstrap function is invalid, then fewer control circuits are needed, but the threshold voltage of the output transistor drifts causing display operation defects
Solution Approach 1:
The patent implements self-service by designing the capacitor to automatically perform the bootstrap function without requiring external control circuits. The capacitor inherently maintains the pull-up node potential through its charging and discharging cycles, which self-regulates the gate-source voltage of the output transistor, preventing threshold voltage drift and ensuring stable display operation without additional complex control mechanisms.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design ensures the bootstrap function of the capacitor is always valid during gate signal output, maintaining a high potential at the pull-up node and preventing abnormal display operations, thereby ensuring normal display screen performance.
Implementation Method 1
a first capacitor, coupled between a signal output terminal of the shift register and the pull-up node
Data Source
Figure 1
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Figure 3~4
AI summary
A shift register and a method for driving the same, a gate driving circuit, and a display device, the shift register includes: a pull-up node control circuit (101) allowing a potential of a pull-up node (PU) to become high according to a first input signal (INPUT 1) and a second input signal (INPUT2); a first capacitor (C1) coupled between a signal output terminal (OUTPUT) and the pull-up node (PU) of the shift register; a pull-down node control circuit (102) controlling a potential of the pull-down node (PD) according to the second clock signal (CK2) and the third clock signal (CK3) and the potential of the pull-up node (PU); an output circuit (103) controlling an output of a gate driving signal at the signal output terminal (OUTPUT) according to the potential of the pull-up node (PU) and a first clock signal (CK1); and a pull-down circuit (104) allowing the potential of the pull-up node (PU) and a potential of the signal output terminal (OUTPUT) to become low according to the potential of the pull-down node (PD).