Shift Register Pull-Down Circuit for Uniform Low Grayscale PWM Control
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Solution Overview
Problem
Existing shift register circuits used in gate drivers for display panels with self-light emitting devices, such as LEDs, face challenges in maintaining uniform luminance at low grayscales due to non-uniform pulse widths of emission control signals across different pixel rows when high-frequency PWM signals are used.
Innovation Solution
The proposed shift register includes an input circuit, a control circuit, an output circuit, and a pull-down control circuit. The pull-down control circuit is designed to control the level at the fifth node regardless of the first clock signal, ensuring proper signal output even when both clock signals are at an inactive level.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If high-frequency PWM signals are used to control LED emitting time, then low grayscale display is achieved, but non-uniform pulse widths occur across different pixel rows causing luminance non-uniformity
Solution Approach 1:
The shift register is divided into multiple stages (first shift register stage, second shift register stage, etc.) that operate independently but synchronously. Each stage has its own clock signal terminal and control circuit, allowing independent control of pulse width for each pixel row while maintaining overall synchronization. This segmentation enables precise control of PWM signals for low grayscale display without luminance non-uniformity.
Solution Approach 2:
The control circuit generates clock signals in advance based on the scanning start signal and pixel row position before the actual PWM signal transmission begins. This preliminary generation of timing signals ensures that each pixel row receives the correct pulse width control signal at the appropriate time, preventing non-uniform luminance while maintaining consistent PWM control across all rows.
2Adaptability or versatility
If existing shift register circuits are used with high-frequency PWM signals, then PWM control is possible, but signal interference occurs and pulse widths become non-uniform
Solution Approach 1:
A control circuit is introduced as an intermediary between the scanning start signal and the PWM signal transmission. This control circuit generates intermediate clock signals that coordinate the timing of data input, shift register operation, and PWM signal output. The control circuit acts as a mediator that synchronizes all operations and prevents signal interference between different control functions.
Solution Approach 2:
The control circuit receives feedback from the scanning start signal and dynamically adjusts the timing of clock signals and data transmission based on the current pixel row position. This feedback mechanism ensures that PWM signals are transmitted at the correct timing without interference from other control signals, maintaining consistent pulse widths across all pixel rows while enabling PWM control capability.
Data Source
AI summary
A shift register includes: an input circuit for transmitting an input signal to a first node under control of a first clock signal, and for transmitting the first clock signal to the second node under control of a level of the first node; a control circuit for transmitting a second power supply signal to the first node under control of a level of the second node and a second clock signal, for transmitting the second clock signal to the third node under control of a level of the fourth node and/or the first; a pull-down control circuit; and an output circuit for transmitting the fourth power supply signal or the third power supply signal to the signal output terminal. The pull-down control circuit controls a level of the fifth node regardless of the first clock signal.