Shift Register Pull-Down Circuit Design for LCD Power and Feed-Through

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional LCD devices face increased power consumption and potential pull-down operation failures due to high-frequency clock signals, which also lead to display quality issues from feed-through effects, as the characteristics of transistor switches degrade over time.

Innovation Solution

A shift register design utilizing a plurality of serially-coupled units with a pull-up driving circuit, high-frequency pull-up circuits, and low-frequency pull-down circuits, along with a fast pull-down circuit to manage voltage levels and compensate for feed-through effects using low-frequency clock signals and feedback voltages.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Speed

If high-frequency clock signals are used to drive pull-down circuits, then the shift register can operate at high speed, but power consumption increases and transistor characteristics degrade over time

Engineering Contradiction:
Improveshift register operating speedVSAvoidpower consumption
Core Design Contradiction:
SpeedVSUse of energy by moving object

Solution Approach 1:

The invention divides the pull-down operation into two distinct circuits: a first pull-down circuit that operates at high frequency during active driving periods, and a second pull-down circuit that operates at low frequency during non-driving periods. This segmentation allows the system to maintain high-speed operation when needed while reducing power consumption during idle periods by switching to the low-frequency circuit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention implements periodic switching between the first and second pull-down circuits based on the driving period of the shift register. During active driving periods, the high-frequency first pull-down circuit is engaged; during non-driving periods, the low-frequency second pull-down circuit is engaged. This periodic action optimizes the balance between speed and power consumption.

Inventive Principle:
Principle #19Periodic action

2Speed

If high-frequency clock signals are used to drive pull-down circuits, then the shift register can operate at high speed, but pull-down operation failures occur due to transistor characteristic degradation

Engineering Contradiction:
Improveshift register operating speedVSAvoidpull-down operation reliability
Core Design Contradiction:
SpeedVSReliability

Solution Approach 1:

The invention divides the pull-down operation into two distinct circuits: a first pull-down circuit that operates at high frequency during active driving periods, and a second pull-down circuit that operates at low frequency during non-driving periods. This segmentation allows the system to maintain high-speed operation when needed while reducing power consumption during idle periods by switching to the low-frequency circuit.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The invention prepares for potential transistor degradation by having a second pull-down circuit ready as a backup. When the first pull-down circuit shows signs of failure or during non-critical periods, the system can switch to the second circuit, providing a cushion against complete failure and ensuring continuous reliable operation.

Inventive Principle:
Principle #11Beforehand cushioning (Prior cushioning)

3Speed

If high-frequency clock signals are used, then the shift register operates faster, but feed-through effects cause display quality issues

Engineering Contradiction:
Improveshift register operating speedVSAvoidfeed-through effects
Core Design Contradiction:
SpeedVSObject-generated harmful factors

Solution Approach 1:

The invention extracts and isolates the feed-through effect problem by implementing a dedicated third pull-down circuit specifically designed to counteract this harmful effect. This separate circuit allows the system to address the feed-through issue independently without compromising the high-speed operation of the main shift register.

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The invention converts the harmful feed-through effect into a controllable parameter by using the third pull-down circuit to intentionally apply compensating signals. What was originally a harmful parasitic effect is now managed and utilized to improve display quality by counteracting the feed-through during critical periods.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

4Reliability

If multiple pull-down circuits are added to reduce power consumption and improve reliability, then system complexity increases

Engineering Contradiction:
Improvepull-down operation reliabilityVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention designs the multiple pull-down circuits to be functionally similar in structure but differentiated in operating frequency and activation timing. This universal design approach allows the circuits to be implemented using the same basic transistor configurations, reducing the actual complexity increase despite having multiple circuits. Each circuit serves a specific temporal function but shares common design principles.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS8483350B2Shift register of LCD devices
Publication Date: 2013.07.09 AU OPTRONICS CORP
  • US8483350B2 patent drawing
  • US8483350B2 patent drawing
  • US8483350B2 patent drawing

AI summary

A shift register includes a plurality of shift register units coupled in series. Each shift register unit, receiving an input voltage at an input end and an output voltage at an output end, includes a node, a pull-up driving circuit, a pull-up circuit and first through third pull-down circuits. The pull-up driving circuit can transmit the input voltage to the node, and the pull-up circuit can provide the output voltage based on a high-frequency clock signal and the input signal. The first pull-down circuit can provide a bias voltage at the node or at the output end based on a first low-frequency clock signal. The second pull-down circuit can provide a bias voltage at the node or at the output end based on a second low-frequency clock signal. The third pull-down circuit can provide a bias voltage at the node or at the output end based on a feedback voltage.