Shift Register Pull-Down Control for Display Stability
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Solution Overview
Problem
In gate driving circuits, the reset signal terminal of a shift register in one stage is coupled to the signal output terminal of the next stage, leading to instability if the next stage's output is abnormal, causing the present stage to fail in completing its pull-down period and resulting in abnormal gate driving circuit outputs.
Innovation Solution
The shift register design includes a pull-down control sub-circuit that allows the first node to disconnect from the second node during the pull-down period, using a pull-down control sub-circuit to manage the potential on the pull-up node and output a low-level voltage, ensuring the pull-down period is independent of other stages' signals, and incorporates a filter sub-circuit to improve signal quality and a residual charge elimination sub-circuit to maintain stability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the reset signal terminal of a shift register in one stage is coupled to the signal output terminal of the next stage, then the circuit structure is simplified and stages are interconnected, but the pull-down period becomes dependent on other stages' signals causing instability and abnormal outputs
Solution Approach 1:
The patent divides the shift register operation into distinct time periods: pull-down period, input period, and output period. During the pull-down period, the first node is disconnected from the second node, making the pull-down operation independent of other stages. This temporal segmentation resolves the contradiction by ensuring reliability during critical operations while maintaining simplified inter-stage coupling for overall circuit structure.
Solution Approach 2:
The patent performs the pull-down operation at the beginning of each cycle before the input and output operations. By completing the pull-down action preliminarily and independently (with disconnection from the second node), the circuit ensures stable initialization of nodes before subsequent operations that involve inter-stage signaling, thus preventing propagation of abnormalities.
2Productivity
If the first node is connected to the second node during all periods, then signal transmission between stages is continuous, but abnormal outputs from the next stage can propagate to the present stage causing chain failures
Solution Approach 1:
The patent dynamically controls the connection state between the first node and second node based on the operational period. During the pull-down period, the connection is disconnected to prevent abnormal signal propagation. During input and output periods, the connection is established to enable normal signal transmission. This dynamic switching resolves the contradiction between continuous transmission and abnormal propagation resistance.
Solution Approach 2:
The patent implements periodic connection and disconnection of the first node to the second node according to the cyclic operation periods. The connection is periodically established during input/output phases and periodically disconnected during pull-down phases, creating a rhythmic pattern that ensures both signal transmission continuity when needed and isolation when preventing abnormal propagation.
3Reliability
If the pull-down period is independent of other stages, then stability is improved, but additional control circuits are required increasing device complexity
Solution Approach 1:
The patent merges the timing control function into the existing periodic operation framework of the shift register. The disconnection of the first node from the second node during the pull-down period is achieved by integrating the control logic with the natural cyclic operation (pull-down, input, output periods) rather than adding independent control circuits. This merging approach achieves pull-down independence without proportionally increasing overall circuit complexity.
Data Source
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AI summary
A shift register, comprising: a first input sub-circuit 10 connected to a first signal end S1, a first voltage end V1 and a first node A, the first input sub-circuit 10 being configured to output a voltage at the first signal end S1 to the first node A; a pull-up control sub-circuit 20 connected to the first node A, a second voltage end V2 and a second node B, the pull-up control sub-circuit 20 being configured to be in an ON or OFF state under the control of the voltage at the first node A and to output the voltage at the second voltage end V2 to the second node B when the pull-up control sub-circuit 20 is in an ON state; and a pull-down control sub-circuit 30 connected to the first node A, a third voltage end V3, a first clock signal end (CKB), a signal output end (Oput) and a pull-down node (PD), the pull-down control sub-circuit 30 being configured to: output the voltage at the third voltage end V3 to the pull-down node (PD), under the control of the voltage at the first node A; output the voltage at the third voltage end V3 to the pull-down node (PD), under the control of the voltage at the signal output end (Oput); and output the voltage at the first clock signal end (CKB) to the pull-down node (PD) under the control of the voltage at the first clock signal end (CKB).