Shift Register Pull-Down Circuit for Display Mode Signal Stability

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Solution Overview

Problem

In shift registers, the long duration of the high floating state of the driving control signal in 2D display mode leads to noise interference and incorrect operation, causing abnormal display and instability.

Innovation Solution

The shift register incorporates a main pull-down unit with sub-pull-down units controlled by specific gate-terminal signals for both 2D and 3D display modes, reducing the high floating state duration by implementing three-pull-down-one and seven-pull-down-one operations, respectively, to stabilize the driving control signal.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If the driving control signal is pulled down by the pull-down circuit controlled by gate-terminal signal G(n+6) in 2D display mode, then the signal timing follows the conventional waveform, but the high floating state duration becomes excessively long (five pulse-widths), causing noise interference and display abnormalities

Engineering Contradiction:

Improveoperational stabilityVSAvoidnoise interference

Core Design Contradiction:

ReliabilityVSObject-affected harmful factors

Solution Approach 1:

The pull-down function is segmented into multiple sub-pull-down circuits (first sub-pull-down circuit controlled by G(n+2) and second sub-pull-down circuit controlled by G(n+6)), each activated at different timing points to collectively reduce the high floating state duration without compromising signal stability

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The first sub-pull-down circuit is activated earlier (by G(n+2)) to preliminarily pull down the driving control signal before the second sub-pull-down circuit (controlled by G(n+6))), thereby reducing the high floating state duration and preventing noise interference in advance

Inventive Principle:

Principle #10Preliminary action

2Manufacturing precision

If the driving control signal Q(n) is pulled up by charging a capacitor in the pull-up circuit when gate-terminal signal G(n) rises, then the signal follows the conventional waveform, but in 2D mode the signal rises too early (two pulse-widths before G(n)) and falls too late (five pulse-widths after G(n))

Engineering Contradiction:

Improvesignal timing precisionVSAvoiddisplay accuracy

Core Design Contradiction:

Manufacturing precisionVSReliability

Solution Approach 1:

The pull-down timing is made dynamic by using different gate-terminal signals (G(n+2) and G(n+6)) for different display modes, allowing the driving control signal timing to be adjusted adaptively to achieve precise timing (rising one pulse-width before G(n) and falling one pulse-width after G(n)))

Inventive Principle:

Principle #15Dynamics

Solution Approach 2:

The timing parameters of the driving control signal are changed by selectively activating different sub-pull-down circuits based on display mode, transforming the signal timing characteristics to achieve precise control and eliminate display abnormalities

Inventive Principle:

Principle #35Parameter changes

3Duration of action of stationary object

If the pull-up circuit remains turned on for a long duration in 2D display mode, then the driving control signal maintains high level, but the pull-down circuit is kept off for too long, preventing the signal from returning to low level and causing pixel activation at wrong time points

Engineering Contradiction:

Improvepull-up circuit on durationVSAvoidpixel activation accuracy

Core Design Contradiction:

Duration of action of stationary objectVSReliability

Solution Approach 1:

The first sub-pull-down circuit provides preliminary anti-action by activating earlier (controlled by G(n+2))) to counteract the prolonged pull-up effect, ensuring the driving control signal returns to low level at the correct time and preventing incorrect pixel activation

Inventive Principle:

Principle #9Preliminary anti-action

Data Source

PatentUS9711079B2Shift register pulling control signals according to display mode

Publication Date: 2017.07.18 AU OPTRONICS CORP

AI summary

A shift register includes a first voltage stabilizing unit, a second voltage stabilizing unit, a main pull-down unit and a main pull-up unit. The first voltage stabilizing unit is used to pull a first driving control signal to a low voltage terminal when a first stabilizing control signal is high. The second voltage stabilizing unit is used to pull the first driving control signal to the low voltage terminal when a second stabilizing control signal is high. The main pull-down unit includes a first sub-pull-down unit controlled by a second gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a first display mode, and a second sub-pull-down unit controlled by a third gate-terminal signal for pulling down the first driving control signal to the low voltage terminal during a second display mode. The main pull-up unit is used for pulling up a first gate-terminal signal.