Shift Register Unit Pulse Width Adjustment
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Solution Overview
Problem
Display devices using GOA technology face difficulties in adjusting the pulse width of gate scanning signals, which is essential for optimizing display performance and reducing manufacturing costs.
Innovation Solution
A shift register unit comprising a first control circuit, pull-down control circuit, energy storage circuit, and output circuit, along with specific transistor configurations, allows for precise control of node potentials to adjust the pulse width of gate scanning signals, enabling flexible signal output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If GOA technology is used to integrate gate driving circuits onto array substrate, then manufacturing cost is reduced and narrow frame design is enabled, but the pulse width of gate scanning signal cannot be adjusted
Solution Approach 1:
The patent introduces controllable circuits that dynamically adjust the pulse width of gate scanning signals. Specifically, control circuits respond to control signals to extend or reduce the duration of gate scanning signals, enabling adaptive pulse width adjustment while maintaining the integrated GOA architecture.
Solution Approach 2:
The patent changes the temporal parameter (pulse width) of the gate scanning signal through controlled potential changes in circuit nodes. By manipulating the potential of specific nodes through control circuits, the signal duration can be extended or reduced according to different display requirements.
2Device complexity
If traditional shift register circuits are used in GOA technology, then circuit integration is achieved, but signal output control flexibility is limited
Solution Approach 1:
The patent segments the shift register circuit into distinct functional modules: clock signal writing circuits, pull-down control circuits, energy storage circuits, and output circuits. Each module performs a specific function, allowing independent control and optimization of signal output characteristics while maintaining overall circuit integration.
Solution Approach 2:
The patent introduces intermediate control nodes and control circuits that mediate between the clock signal input and the final signal output. These intermediate elements provide additional control points that enhance flexibility in signal output timing and duration without compromising circuit integration.
Data Source
AI summary
A shift register unit and a control method thereof, a gate driving circuit, and a display device are provided. The shift register unit comprises: a first control circuit (110) and an energy storage circuit (150), which directly control the potential of a first node (Q1); a pull-down control circuit (120), a second control circuit (130) and a first pull-down circuit (140), which indirectly control the potential of the first node (Q1); and an output circuit (160), which outputs, under the control of the potential of the first node (Q1), a first voltage signal provided by a first voltage end (VDD) to a signal output end. By means of the shift register unit, the control method thereof and the gate drive circuit, the pulse width of a gate scanning signal can be adjusted, thereby meeting various display requirements.