Shift Register Pulse Width Modulation for Display Flicker Reduction
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Solution Overview
Problem
Existing gate driver on array (GOA) circuits experience flicker phenomena during low gray-scale brightness adjustments due to large output pulse widths of shift registers, affecting display quality.
Innovation Solution
A shift register design incorporating an input module, output module, potential maintenance module, and pulse width modulation module, where pulse width modulation submodules adjust the output pulse width by controlling clock and enable signals, reducing the pulse width by 1/(n+1) to (n−1)/(n+1) clock cycles without altering light emitting duration, thereby increasing refresh rate and minimizing flicker.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Duration of action of moving object
If the output pulse width of the shift register is large, then the light emitting time of pixels is sufficient, but a flicker phenomenon occurs during low gray-scale brightness adjustment
Solution Approach 1:
The patent applies periodic action by using multiple clock signal terminals (first clock signal terminal, second clock signal terminal, and other clock signal terminals) that jump successively to the first level, creating periodic pulse width modulation cycles. This periodic structure allows the output pulse width to be divided into multiple sub-cycles, reducing the visible flicker effect while maintaining sufficient total light emitting time for pixel activation.
Solution Approach 2:
The patent implements dynamics by making the pulse width modulation adjustable through multiple enable signal terminals and clock signal terminals. The system can dynamically adjust the output pulse width by controlling which clock cycles are activated, allowing optimization between light emitting duration and flicker reduction based on different operating conditions and gray-scale requirements.
2Productivity
If the output pulse width is reduced to eliminate flicker, then the refresh rate increases, but the light emitting duration may be insufficient
Solution Approach 1:
The patent applies segmentation by dividing the output pulse width into multiple discrete clock cycles controlled by different clock signal terminals and enable signal terminals. Each clock cycle represents a segment that can be independently controlled, allowing the total light emitting duration to be distributed across multiple segments while maintaining a high refresh rate through periodic activation of these segments.
Solution Approach 2:
By using periodic action with multiple clock signal terminals that jump successively, the patent creates a rhythm of pulse activation that increases the effective refresh rate. The periodic structure ensures that while individual pulse widths are reduced, the cumulative light emitting time across multiple periods remains sufficient for proper pixel activation.
Data Source
AI summary
The disclosure relates to a shift register, a driving method thereof, a gate drive circuit, and a display device. An output pulse width can be reduced by 1/(n+1) to (n−1)/(n+1) clock cycle by setting a pulse width modulation module (104), where n is the number of clock signal terminals in one-to-one correspondence with the enable signal terminals, and the pulse width reduced by 1/(n+1) to (n−1)/(n+1) clock cycle needs to be output several times under the condition that the light emitting duration of pixels is unchanged. In this way, the refresh rate is increased, and thus the flicker phenomenon in the process of low gray-scale brightness adjustment is less detectable to the human eyes.