Shift Register PWM Circuit for Gate Pulse Width Control

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Solution Overview

Problem

Current display technologies, particularly AMOLED displays, face challenges in controlling the pulse width of gate driving signals and light emitting control signals, which affects the working performance of pixel driving circuits.

Innovation Solution

A shift register unit with a PWM function is introduced, comprising an input circuit, capacitor circuits, output circuits, and inverter circuits, allowing for the control of pulse widths of output signals through specific phase control and signal connections, enabling adjustable pulse widths for gate driving signals and light emitting control signals.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If a conventional gate driving circuit is used, then the circuit structure is simple, but the pulse width of gate driving signals cannot be controlled

Engineering Contradiction:
Improvepulse width control capabilityVSAvoidcircuit structure
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent combines the shift register function with PWM control function into a single integrated circuit. The shift register unit includes input circuits, capacitor circuits, output circuits, and inverter circuits that work together to generate gate driving signals with controllable pulse widths, eliminating the need for separate PWM control circuits.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The shift register unit is designed to perform multiple functions: signal shifting, signal buffering, and PWM pulse width modulation. By incorporating control terminals (such as the fourth control terminal) and associated control circuits, the same circuit structure can generate different pulse widths for gate driving signals based on control voltage levels.

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If the pulse width of gate driving signals is adjusted, then the working performance of pixel driving circuits is optimized, but the control complexity increases

Engineering Contradiction:
Improvepixel driving performanceVSAvoidcontrol circuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The shift register unit automatically adjusts the pulse width of gate driving signals based on control voltages applied to its control terminals. The internal capacitor circuits and inverter circuits self-regulate the signal timing and duration, eliminating the need for external complex control logic or additional timing circuits.

Inventive Principle:
Principle #25Self-service

3Illumination intensity

If a PWM function is added to control light emitting signals, then the display quality is improved, but the device complexity increases

Engineering Contradiction:
Improvedisplay qualityVSAvoidcontrol circuit
Core Design Contradiction:
Illumination intensityVSDevice complexity

Solution Approach 1:

The patent integrates PWM control for light emitting signals within the shift register unit. The same capacitor circuits and inverter circuits that control gate driving signals also control light emitting control signals, allowing pulse width modulation for both signal types without requiring separate PWM control circuits.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS11961466B2Shift register unit, driving method thereof, gate driving circuit, and display device
Publication Date: 2024.04.16 HEFEI BOE ZHUOYIN TECH CO LTD
  • US11961466B2 patent drawing
  • US11961466B2 patent drawing
  • US11961466B2 patent drawing

AI summary

A shift register unit and a driving method thereof, a gate driving circuit, and a display device. The shift register unit includes: an input circuit, a first capacitor circuit, an output circuit, an output pull-down circuit, a coupling circuit, and an inverter circuit. The inverter circuit is coupled to an input control terminal, a first node, a second node, and a first level signal input terminal, and a second level signal input terminal; and used to control to connect or disconnect the second node and the first level signal input under the control of the input control terminal and the first level signal input terminal; also used to control to connect or disconnect the second node and the second level signal input terminal under the control of the first node and the second level signal input terminal.