Shift Register Cascade Control for Area-Specific Refresh Rates

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Solution Overview

Problem

Existing display technologies face challenges in achieving high integration and low cost while efficiently managing different refresh rates in various areas of a display panel, leading to increased power consumption and complexity in control wiring.

Innovation Solution

A shift register design incorporating a shift module, reverse output module, latch module, and selection output module, which allows for dynamic control of refresh rates by utilizing phase differences in cascade signals and a single masking signal, reducing power consumption and simplifying control wiring.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Device complexity

If a single masking signal is used to control refresh rates, then control wiring is simplified, but the ability to manage different refresh rates in various areas is limited

Engineering Contradiction:
Improvecontrol wiringVSAvoidrefresh rate control capability
Core Design Contradiction:
Device complexityVSAdaptability or versatility

Solution Approach 1:

The shift register is divided into multiple stages, with each stage capable of independently controlling refresh rates for different display areas. The cascade signal output end of each stage connects to the input signal end of the next stage, creating segmented control zones that can operate at different refresh rates simultaneously

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The circuit uses dynamic signal routing through switching transistors that can change states based on cascade signals and power supply voltages. This allows the same masking signal to dynamically control different refresh rates in different areas by leveraging the phase differences in cascade signals from previous stages

Inventive Principle:
Principle #15Dynamics

2Reliability

If high refresh rates are maintained across the entire display panel, then display quality is improved, but power consumption increases

Engineering Contradiction:
Improvedisplay qualityVSAvoidpower consumption
Core Design Contradiction:
ReliabilityVSUse of energy by moving object

Solution Approach 1:

Different areas of the display panel can operate at different refresh rates based on their specific requirements. Areas requiring high refresh rates for motion clarity can maintain high rates, while static areas can operate at lower rates, optimizing overall power consumption while preserving display quality where needed

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The circuit utilizes periodic clock signals and cascade signals with different phases to control the switching transistors. By synchronizing refresh operations with these periodic signals, the system can dynamically adjust refresh rates in different areas, reducing power consumption during periods when high refresh rates are not necessary

Inventive Principle:
Principle #19Periodic action

3Adaptability or versatility

If multiple masking signals are used to control different refresh rates, then refresh rate management is improved, but device complexity increases

Engineering Contradiction:
Improverefresh rate managementVSAvoidcontrol wiring
Core Design Contradiction:
Adaptability or versatilityVSDevice complexity

Solution Approach 1:

A single masking signal serves multiple functions by being processed through different stages of the shift register, each stage utilizing the phase differences in cascade signals to create area-specific refresh rate control. This multi-functional approach eliminates the need for separate masking signals for each display area

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS12361894B2Shift register, driving method, gate drive circuit and display device
Publication Date: 2025.07.15 CHENGDU BOE OPTOELECTRONICS TECH CO LTD
  • US12361894B2 patent drawing
  • US12361894B2 patent drawing
  • US12361894B2 patent drawing

AI summary

A shift register includes a shift module configured for causing the cascade signal output end to output a cascade signal in response to a signal of the input signal end; an reverse output module configured for causing the reverse signal output end to output a signal reverse to the cascade signal output end in response to a signal of the cascade signal output end; a latch module configured for causing an output end of the latch module to output a control signal of the masking signal end in response to signals of the cascade signal output end and the reverse signal output end of a previous level; and a selection output module configured for providing a signal of the first power supply end or the second power supply end to the driving signal output end in response to a signal of the output end of the latch module.