Shift Register Reset Logic for Gate Driver Signal Discharge
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Solution Overview
Problem
In existing display devices, the shift registers used in gate drivers struggle to quickly discharge output signals from a high state to a low state, leading to image deterioration due to delayed signal discharge, which affects the reliability of the gate driver and display device.
Innovation Solution
The method involves configuring shift registers such that an Nth shift register is reset by an (N+2)th shift register's output signal, allowing for sequential charging, outputting high-state signals during specific clock periods, and rapid discharge to a low state during subsequent clock periods, using a cascade connection with specific clock phases to prevent signal overlap and improve discharge efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the Nth shift register is reset by the (N+1)th shift register's output signal in a cascaded manner, then the device complexity is reduced and manufacturing is simplified, but the output signal cannot be discharged quickly leading to image deterioration
Solution Approach 1:
The shift register system is segmented into multiple independent shift registers (1st to (N+2)th) with distinct functions. The Nth shift register is separated from the dummy shift register by introducing an (N+1)th shift register, allowing the Nth register to be reset by the (N+2)th register's output. This segmentation enables independent optimization of each register's discharge timing, resolving the contradiction between simplified cascaded configuration and rapid signal discharge.
Solution Approach 2:
The (N+2)th shift register performs preliminary action by generating the reset signal one clock cycle earlier than the traditional dummy register. This advance preparation allows the Nth shift register to discharge its output signal completely before the next signal cycle begins, preventing the overlapping and image deterioration that occurs in traditional cascaded configurations.
2Ease of operation
If shift registers operate in synchronization with clock signals in a cascaded manner, then ease of operation is improved, but signal discharge is delayed causing image deterioration
Solution Approach 1:
The system uses periodic clock signals (first clock and second clock with opposite phases) to drive the shift registers in a structured periodic manner. Each shift register operates during specific clock periods, with the Nth register discharging during the third clock period and being reset during the fourth clock period. This periodic action pattern ensures complete signal discharge within each cycle while maintaining ease of operation through synchronized clocking.
Solution Approach 2:
The reset timing is made dynamic by having the Nth shift register reset by the (N+2)th register's output rather than a fixed dummy register. This dynamic configuration allows the reset signal to arrive at the optimal moment for complete signal discharge, adapting the timing to the actual signal propagation characteristics and eliminating the time loss associated with fixed cascaded timing.
3Device complexity
If the dummy shift register resets the last shift register, then the system structure is simplified, but signal overlap occurs leading to image deterioration
Solution Approach 1:
The (N+1)th shift register serves as an intermediary between the Nth shift register and the (N+2)th shift register. Instead of the (N+2)th register directly resetting the Nth register (which would cause timing conflicts and signal overlap), the (N+1)th register mediates the reset signal transmission. This intermediary structure prevents signal overlap while maintaining a relatively simple system configuration, as the intermediary register naturally spaces out the reset timing.
Data Source
AI summary
A gate driver, comprises a plurality of shift registers configured to output signals sequentially such that an Nth shift register is reset by an output signal of an (N+2)th shift register, wherein last, second last and third last shift registers are reset by a last output signal of the last shift register.