Shift Register Unit Reset Phase Segmentation for Display Driving
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Solution Overview
Problem
Display apparatuses with higher resolution require longer reset time intervals for gate driving signals, leading to shorter time intervals for pixel charging, which is unfavorable for pixel charging efficiency.
Innovation Solution
A shift register unit with a working cycle comprising an input phase, output phase, reset phase, and maintaining phase, where the gate driving signal is pulled down to a reference voltage and then to a gate-off voltage, reducing the reset time interval and ensuring stable operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the display apparatus has higher resolution, then the display quality is improved, but the reset time interval becomes longer which reduces pixel charging time
Solution Approach 1:
The reset phase is segmented into two distinct stages: first pulling the output terminal voltage down to a reference voltage (first reset signal), then pulling it down further to a gate-off voltage (second reset signal). This segmentation allows optimized timing for each stage, reducing the overall reset time while maintaining display quality.
Solution Approach 2:
The gate driving signal is preliminarily pulled down to the reference voltage during the first reset phase before the final pull-down to gate-off voltage. This preliminary action prepares the signal in advance, enabling faster transition and reducing the total reset time interval, thereby increasing pixel charging time.
2Reliability
If the reset time interval is extended for high resolution displays, then the gate driving signal reset is more complete, but the pixel charging time interval becomes shorter
Solution Approach 1:
The reset operation is divided into two phased segments with different duration and voltage target requirements. The first segment pulls voltage to reference level with moderate timing, the second segment completes the pull-down to gate-off voltage. This segmentation ensures reliable reset completion while minimizing total time consumption.
Solution Approach 2:
The patent introduces a reference voltage parameter that is higher than the gate-off voltage but lower than the gate-on voltage. By using this intermediate reference voltage as a temporary target during reset, the signal transitions are optimized to achieve both completeness and speed, balancing reliability with time efficiency.
3Device complexity
If a simple reset mechanism is used, then the device complexity is reduced, but the reset time cannot be sufficiently shortened for high resolution displays
Solution Approach 1:
The reset mechanism uses segmentation of control signals (first reset signal and second reset signal) rather than complex hardware circuits. This signal-based segmentation achieves fast reset timing with minimal additional device complexity, as it leverages existing transistor switching capabilities.
Solution Approach 2:
The shift register unit uses its own internal transistors and nodes (output terminal, pull-up node) to perform the reset operation without requiring external reset circuitry. The segmented reset signals are generated and applied within the unit itself, achieving fast reset with no additional external complexity.
Data Source
AI summary
Disclosed is a shift register unit, a gate driving circuit and a driving method, as well as a display apparatus. The shift register unit has a working cycle including an input phase, an output phase, a reset phase and a maintaining phase. In the reset phase, a clock signal is transmitted to an output terminal to pull a voltage of the output terminal down to a reference voltage, and the pulled-down voltage of the output terminal is subsequently changed from the reference voltage to a gate-off voltage. In the maintaining phase, the voltage of the output terminal is maintained at the gate-off voltage. The reference voltage is smaller than the gate-off voltage.