Shift Register Unit Reset Signal Elimination
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Solution Overview
Problem
The complexity of connection lines among shift register units in gate driving circuits complicates the design, making it difficult to achieve a narrow frame in display products, as existing designs require separate reset signal lines.
Innovation Solution
A shift register unit design that integrates an input module, an output module, and an output control module, eliminating the need for a separate reset module and thus eliminating the need for reset signal lines, simplifying the connection design and reducing the area required for shift register units.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a separate reset module and reset signal lines are used in shift register units, then the reset function can be achieved, but the connection lines become complex and the frame width increases
Solution Approach 1:
The patent merges the reset function into the existing clock signal transmission path by using the clock signal to control both signal transmission and reset operations. The clock signal terminal serves dual purposes: transmitting control signals to the next stage and resetting the current stage when needed, eliminating the need for separate reset signal lines and reducing connection complexity.
Solution Approach 2:
The clock signal is given multi-functionality by using it for both normal signal transmission and reset operations. The same clock signal terminal and wiring are used to achieve both functions, thereby eliminating dedicated reset lines and simplifying the overall connection structure while maintaining reliable reset capability.
2Reliability
If reset signal lines are added among shift register units, then the reset function is achieved, but the area occupied by connection lines increases
Solution Approach 1:
The reset function is merged with the existing clock signal transmission infrastructure. By using the clock signal terminal and existing wiring to perform reset operations, the patent eliminates the need for additional reset signal lines, thereby reducing the area occupied by connection lines while maintaining reliable reset functionality.
Solution Approach 2:
The clock signal terminal and connection lines are designed to serve multiple functions: normal signal transmission and reset operations. This multi-functionality approach allows the same physical infrastructure to achieve both purposes, significantly reducing the total area required for connection lines.
3Reliability
If separate reset modules are designed for each shift register unit, then reset control is achieved, but the device structure becomes complex
Solution Approach 1:
The patent merges the reset control function with the existing clock signal control mechanism. The clock signal terminal and associated control logic handle both normal operation and reset control, eliminating the need for separate reset modules and simplifying the overall device structure while maintaining reliable reset control.
Solution Approach 2:
The clock signal control system is designed to perform multiple functions including normal signal transmission and reset control. By making the clock signal terminal and control logic multi-functional, the patent reduces device structural complexity while ensuring reliable reset control capability.
Data Source
AI summary
Embodiments of the present disclosure provide a shift register unit, a gate driving circuit, a driving method and a display apparatus, which can simplify the design of connection lines among the shift register units and thereby is beneficial to achieve a narrow frame of the product. The shift register unit comprises an input module connected to an input terminal, a first control signal terminal and a first node; an output module connected to a first node, a second node, a second control signal terminal, an output terminal and a second level terminal; and an output control module connected to the first node, the second node, the output terminal, a first level terminal and the second level terminal. The embodiments of the present disclosure are used to manufacture displays.


