Shift Register Circuit Reverse Clock Input for GOA Signal Delay
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Solution Overview
Problem
In display panels using Gate Driving On Array (GOA) technology, the transition of resistive and capacitive loads at the boundary of adjacent GOA blocks leads to signal delay, resulting in display issues like flickers, stripes, and mura due to block driving techniques.
Innovation Solution
A shift register circuit design where adjacent drivers receive clock driving signals in reverse directions, with input wiring configurations and compensation resistors arranged to minimize load transitions, ensuring consistent signal delivery across the array substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If block driving technique is used to reduce power consumption, then energy efficiency is improved, but signal delay and display issues (flickers, stripes, mura) occur at the boundary of adjacent GOA blocks
Solution Approach 1:
The patent applies inversion by reversing the clock driving signal input direction for adjacent drivers. Specifically, one driver receives clock signals from its first end position to second end position, while the adjacent driver receives clock signals from its second end position to first end position (reverse direction). This inverted approach at the boundary eliminates the transition of resistive and capacitive loads that causes signal delay, while still maintaining block driving for power savings.
2Loss of energy
If GOA blocks are divided for block driving, then power consumption is reduced, but the boundary between blocks causes signal delay due to load transitions
Solution Approach 1:
The patent reverses the clock signal input direction for adjacent GOA blocks to eliminate the harmful transition effect at block boundaries. By having one block input clock signals from top to bottom and the adjacent block from bottom to top, the resistive and capacitive load transitions are canceled out, preventing signal delay while maintaining the power-saving block driving structure.
3Device complexity
If clock driving signals are input in the same direction to adjacent drivers, then wiring is simplified, but signal delay occurs at the boundary due to load transitions
Solution Approach 1:
The patent implements reverse direction input for clock driving signals in adjacent drivers. The first driver receives clock signals from its first end position to second end position, while the second driver receives clock signals from its second end position to first end position. This inversion eliminates the transition effect at the boundary between drivers, preventing display issues like flickers, stripes, and mura, while the wiring complexity increase is minimal and localized to the boundary region.
Data Source
AI summary
The present disclosure provides a shift register circuit, an array substrate, and a display device. For a first driver and a second driver adjacent to each other in a direction substantially perpendicular to the gate line, a first driving input wiring of the first driver is arranged to input a first clock driving signal to individual shift registers successively from a shift register at a first end position of the first driver to a shift register at a second end position of the first driver, and a second driving input wiring of the second driver is arranged to input a second clock driving signal to individual shift registers successively from a shift register at a second end position of the second driver to a shift register at a first end position of the second driver.