Shift Register Unit Segmentation for Gate Line Driving
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Solution Overview
Problem
Existing gate line driving devices have large pull-down transistors with low efficiency, leading to circuit downsizing and power consumption issues, signal delay, and reliability problems due to the shared output transistor handling both signal output and reset functions across stages.
Innovation Solution
The shift register unit design separates the driving signal for the current stage from the trigger and reset signals for the next and previous stages, respectively, and removes the large pull-down transistor, allowing for extended turn-on time of the output transistor to perform pull-down control, reducing signal delay and improving waveform quality, and facilitating easier failure identification.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a large-size pull-down transistor is used to reset the output terminal of the shift register unit, then the reset function is achieved, but the circuit area increases and power consumption increases
Solution Approach 1:
The patent segments the reset function from the pull-down function. The reset transistor (second transistor) is separated from the output transistor (third transistor), allowing the reset function to be performed by a smaller dedicated transistor rather than requiring a large pull-down transistor. This segmentation enables the output transistor to be optimized for drive strength while the reset transistor handles only reset operations, reducing overall circuit area.
Solution Approach 2:
The output transistor (third transistor) is designed to perform multiple functions: driving the gate line signal and assisting in the reset process through its connection with the reset transistor. This multi-functionality reduces the need for separate large pull-down transistors, as the output transistor contributes to both signal output and reset operations, thereby reducing total circuit area and power consumption.
2Device complexity
If the output transistor handles both signal output and reset functions for multiple stages, then device complexity is reduced, but signal delay increases and reliability decreases
Solution Approach 1:
The patent segments the signal output function and reset function into separate transistors (output transistor and reset transistor). This segmentation allows each transistor to be optimized for its specific function, reducing the load on the output transistor and thereby reducing signal delay. The reset transistor handles reset operations independently, preventing reset tasks from slowing down signal output to next stage.
Solution Approach 2:
The reset function is extracted from the output transistor and assigned to a dedicated reset transistor. This extraction reduces the functional load on the output transistor, allowing it to focus on signal output with reduced delay. The separated reset transistor can perform reset operations without interfering with the timing-critical signal output path.
3Device complexity
If the output transistor has a failure, then the gate line corresponding to the current stage is affected, but also the gate lines in previous and next stages are affected
Solution Approach 1:
The patent segments the output function and reset function into separate transistors, creating functional isolation. If the output transistor fails, the reset transistor can still perform reset operations for the current stage and can trigger reset in previous stages through the reset signal path. This segmentation prevents a single point of failure from cascading to all stages, as the reset functionality remains independent and operational.
Solution Approach 2:
The reset transistor acts as an intermediary that can independently initiate reset signals. If the output transistor fails, the reset transistor can still receive reset signals from next stage and propagate them to previous stages, maintaining system reliability. This intermediary reset function breaks the failure cascade that would otherwise occur through the shared output transistor.
Data Source
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AI summary
A shift register unit, a gate line driving device includes multiple stages of the shift register units, and a driving method for being applied to the shift register unit; the shift register unit includes: an input module (200) connected between an input terminal (INPUT) and a pull-up node (PU), and configured to charge the pull-up node (PU); an output module (205) connected between the pull-up node (PU), a first clock signal terminal (CK) and an output terminal (OUTPUT), and configured to output to the output terminal (OUTPUT) a first clock signal received at the first clock signal terminal (CK); a pull-up node reset module (215) connected between a reset terminal (RESET-IN), a pull-down node (PD) and the pull-up node (PU), and configured to reset the pull-up node (PU); and an output reset module (220) connected between a second clock signal terminal (CKB), the pull-down node (PD) and the output terminal (OUTPUT), and configured to reset the output terminal (OUTPUT). The shift register unit, a gate line driving device and a driving method can downsize an overall structure of the GOA, reduce power consumption, decrease signal delay, improve signal waveform, and also enhance reliability of the GOA circuit in entirety.