Shift Register Noise Reduction via Segmented Node Control
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Solution Overview
Problem
Existing shift registers in liquid crystal display panels suffer from noise in scanning signals and high power consumption, which reduces the yield and market competitiveness of display panels.
Innovation Solution
A shift register design incorporating an input module, node pull-up/down modules, output control modules, and an output noise-reduction module, utilizing switching transistors to filter and reduce noise in scanning signals, thereby enabling low-noise signal transmission and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the first node PU pulls up the potential continuously in the first and second stages, then the switching transistor T7 can be turned on, but the scanning signal includes relatively large noise and power consumption increases
Solution Approach 1:
The patent divides the potential control into separate stages: the first node PU handles the first stage pull-up, while the second node P2 handles the second stage pull-up. This segmentation allows independent optimization of each stage's signal characteristics, reducing noise propagation to the scanning signal output.
Solution Approach 2:
The second node P2 acts as an intermediary between the first node PU and the scanning signal output. By introducing this intermediate stage with its own pull-up control, the patent filters and conditions the signal before it reaches the output, reducing noise while maintaining reliable transistor activation.
2Ease of operation
If the first node PU outputs high potential signal, then the switching transistor T7 turns on, but the charging and discharging by capacitor C1 generates large noise in the scanning signal
Solution Approach 1:
The patent separates the capacitor charging function from the scanning signal output path by placing the capacitor C1 at the second node P2 rather than directly at the first node PU. This segmentation isolates the noise-generating charging/discharging events from the main signal transmission path.
Solution Approach 2:
The second node P2 serves as a buffer between the first node PU and the scanning signal output. The capacitor C1 charges and discharges at this intermediate node, absorbing noise before it can propagate to the output, while still enabling proper switching transistor activation.
3Productivity
If the shift register uses traditional circuit structure, then the gate driver function is achieved, but the power consumption is high and yield is reduced
Solution Approach 1:
The patent segments the gate driver function across multiple shift register stages, with each stage independently controlling its switching transistors. This allows for more efficient power management where only necessary transistors are activated at each stage, reducing overall power consumption while maintaining full gate driver functionality.
Data Source
AI summary
A shift register includes an input module, a first and a second node pull-down module, a second node pull-up module, an output control module and an output noise-reduction module. The input module is configured to pull up a potential at a first node, the first node pull-down module is configured to pull down the potential at the first node, the second node pull-up module is configured to pull up a potential at a second node, the second node pull-down module is configured to pull down the potential at the second node, the output control module is configured to control a scanning signal output end to output a signal from the second lock signal end or a low level signal end, and the output noise-reduction module is configured to filter a signal from the first node and decrease a noise therein and output the resultant signal to a third node.