Shift Register Unit With Segmented Pull-Down Circuits
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Solution Overview
Problem
Existing shift register units face poor noise reduction performance due to transistors in the pull-down circuit not being effectively turned on during low clock signals, leading to inadequate pulling of levels at the pull-up node and output end to a low level.
Innovation Solution
The shift register unit incorporates multiple pull-down circuits controlled by sequential clock control signals with time delays, allowing flexible control of noise reduction and independent signal ends for each circuit, ensuring effective noise reduction and improved reliability by alternating the operation of pull-down circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a single pull-down circuit is used in the shift register unit, then the circuit structure is simple, but the noise reduction performance is poor because the transistor cannot be effectively turned on during low clock signals
Solution Approach 1:
The single pull-down circuit is divided into multiple pull-down circuits (first pull-down circuit and second pull-down circuit). Each circuit has its own transistor that can be independently controlled by different clock signals. This segmentation allows at least one transistor to be effectively turned on during both high and low clock signal periods, solving the noise reduction problem while maintaining reasonable circuit complexity through modular design.
Solution Approach 2:
Different clock signals with different phases are applied to control the transistors in different pull-down circuits. During high clock signal periods, one transistor is turned on; during low clock signal periods, the other transistor is turned on. This periodic alternating action ensures continuous effective noise reduction across the entire signal cycle, resolving the contradiction between reliability and complexity.
2Reliability
If multiple pull-down circuits with sequential clock control signals are used, then the noise reduction performance is enhanced, but the control signal complexity increases
Solution Approach 1:
Multiple clock signals with different phases are used to control different pull-down circuits in a periodic manner. The first clock signal controls the first pull-down circuit during high periods, while the second clock signal controls the second pull-down circuit during low periods. This periodic control ensures continuous noise reduction effectiveness while using standard phased clocking techniques that do not significantly increase control complexity.
Solution Approach 2:
The pull-down circuits are pre-configured with their respective clock signal inputs and transistor connections during circuit design. This preliminary arrangement of control signal paths and transistor gating ensures that when the clock signals are applied, the noise reduction function is immediately and effectively activated without requiring complex real-time control logic, thus managing control signal complexity.
Data Source
AI summary
Disclosed is a shift register unit and a driving method therefor. The shift register unit includes an input circuit that is connected to a first input end and a second input end; a pull-up circuit that is connect to an output end; a first pull-down circuit and a second pull-down circuit; and where the input circuit is configured to receive a first power signal, and a second power signal, and the input circuit is controlled by the first power signal and the second power signal; the first pull-down circuit and the second pull-down circuit are connected to the input circuit and the pull-up circuit, and each first pull-down circuit is configured to receive a control signal; and the pull-up circuit is configured to receive a clock signal.