Shift Register Self-Reset Circuit for Gate Array
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Solution Overview
Problem
In liquid crystal display technology, gate on array circuits rely on a driving signal from the next stage to reset the shift register, limiting their ability to perform self-reset functions, which increases complexity and space requirements.
Innovation Solution
A shift register design incorporating a pre-charging module, an output module, a reset module, and a reset control module, where the reset control module uses the driving signal to pull up voltage and output a reset signal, allowing the shift register to reset itself without needing a dummy signal line.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the reset function is realized by using the driving signal from the next stage, then the reset function can be achieved, but the device complexity and space requirements increase
Solution Approach 1:
The shift register is designed to generate its own reset signal using its own output driving signal. The reset control module uses the output signal from the current stage's output signal terminal to control the reset operation, eliminating the need for external reset signals from the next stage. This self-service mechanism reduces device complexity while maintaining the reset function.
Solution Approach 2:
The output signal terminal serves dual purposes: it outputs the driving signal for the next stage and simultaneously provides the signal for generating the reset signal. The reset control module utilizes the output driving signal to control the reset operation, making the output signal terminal multi-functional and reducing the need for additional dedicated reset signal lines.
2Reliability
If the reset function is realized by using the driving signal from the next stage, then the reset function can be achieved, but the space requirements increase
Solution Approach 1:
The shift register generates its own reset signal internally using its own output driving signal. The reset control module is configured to use the output signal from the current stage to control the reset operation, eliminating the need for external reset signal lines from the next stage and reducing the overall circuit area.
Solution Approach 2:
The reset signal generation function is merged with the output signal generation function. The reset control module uses the output driving signal to generate the reset signal, combining multiple functions into a single integrated structure that reduces space requirements compared to having separate dedicated reset signal paths.
3Device complexity
If the shift register uses its own driving signal for reset, then the device complexity is reduced, but the reset timing control becomes more challenging
Solution Approach 1:
The reset control module uses the output driving signal as feedback to control the reset operation. By monitoring the output signal and using it to trigger the reset at the appropriate time, the system achieves precise timing control without requiring complex external timing circuits. The feedback mechanism ensures the reset occurs at the correct phase of the driving cycle.
Solution Approach 2:
The reset signal is generated in advance based on the output driving signal timing. The reset control module is configured to produce the reset signal at the appropriate time relative to the output signal, ensuring that the reset operation is ready and timed correctly before needed, simplifying the overall timing control.
Data Source
AI summary
Provided are a shift register and a driving method thereof, a gate on array circuit and a display apparatus. The shift register includes a pre-charging module, an output module, a reset module and a reset control module. The pre-charging module is configured to charge a first node in a pre-charging period. The output module is configured to pull up a voltage at the first node and output a driving signal through the output signal terminal in an output period. The reset control module is configured to pull up a voltage at the second node by the driving signal outputted through the output signal terminal in the output period and output the voltage at the second node pulled up in the output period to the reset module as a reset signal in a reset period.