Shift Register Circuit Area Reduction via Shared Nodes
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Solution Overview
Problem
The existing gate drive circuits for high-resolution display panels occupy a large area and have a wide border, making it challenging to miniaturize and reduce production costs, especially with the increased complexity of multi-gate drivers like 3G1D layouts.
Innovation Solution
A shift register design that allows multiple output subcircuits to share pull-up and pull-down nodes, reducing the number of circuit devices and simplifying the structure, thereby narrowing the border and minimizing the overall circuit area, while also synchronizing clock signals to ensure consistent transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If multiple output subcircuits each have independent pull-up and pull-down nodes, then each output can be controlled independently, but the number of circuit devices increases and the circuit area expands
Solution Approach 1:
The patent merges multiple independent pull-up and pull-down nodes into shared nodes. Specifically, multiple output subcircuits share common pull-up nodes and pull-down nodes, reducing the total number of circuit devices while maintaining independent control capability through shared control signals.
Solution Approach 2:
The shared pull-up and pull-down nodes serve multiple output subcircuits simultaneously, making these nodes universal resources that perform multiple functions. This multi-functionality reduces device count while preserving independent control through selective activation.
2Manufacturing precision
If each output subcircuit has dedicated control devices, then control precision is high, but device complexity increases
Solution Approach 1:
The patent combines control devices across multiple output subcircuits into shared control structures. Control signals are distributed to multiple output subcircuits through shared control nodes, reducing the total number of control devices while maintaining precise control through signal timing and level management.
3Ease of operation
If clock signals are provided to each output subcircuit independently, then timing control is flexible, but the border width increases
Solution Approach 1:
The patent merges multiple clock signal lines into shared clock signal paths that serve multiple output subcircuits. By providing clock signals through shared nodes rather than dedicated lines to each subcircuit, the border width is reduced while timing control flexibility is maintained through the shared clock distribution network.
Data Source
AI summary
A shift register, a gate drive circuit, a display apparatus and a driving method of the shift register are provided. The shift register includes an input subcircuit, a first and a second output subcircuits, a trigger signal input terminal, a first and a second signal output terminals, a first and a second clock terminals and a pull-up node, a control terminal and an output terminal of the input subcircuit are electrically coupled to the trigger signal input terminal and the pull-up node, respectively, for providing a valid signal received by the control terminal of the input subcircuit to the pull-up node. The shift register is provided with the first and second output subcircuits which share the same input subcircuit, greatly reducing the number of devices and thus greatly simplifying the structure of the cascaded shift registers and reducing the area of the whole display apparatus.