Shift Register Signal Delay Control for Foldable Displays
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Solution Overview
Problem
Foldable displays face challenges with signal delay and poor display quality due to signal distortion in long gate lines, which conventional shift registers and drive methods are unable to effectively address.
Innovation Solution
A shift register design incorporating multiple transistors and capacitors, along with a specific drive method that controls clock signals and selection signals to manage signal delay, is introduced. This design includes a first transistor, second transistor, third transistor, and capacitors, with control electrodes and electrodes connected in a manner that allows for precise control of output signals across multiple phases, improving signal delay management.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If a long gate line is used in large-scale display panels, then the display area can be expanded, but signal distortion occurs and display quality deteriorates
Solution Approach 1:
The gate driver is divided into multiple independent GOA units that are distributed across the display panel. Each GOA unit independently drives a specific region, breaking the long gate line into multiple shorter segments. This segmentation reduces signal distortion in each segment while maintaining coverage of the entire large display area.
Solution Approach 2:
The gate driver structure transitions from a single centralized unit to a two-dimensional array of distributed GOA units across the panel. This spatial distribution across multiple dimensions allows each unit to drive local regions with shorter gate lines, improving signal quality while covering the entire large display area.
2Device complexity
If conventional shift registers are used in foldable displays, then the structure can be simple, but signal delay cannot be effectively controlled
Solution Approach 1:
The shift register incorporates controllable delay circuits with adjustable delay amounts. The delay time can be dynamically adjusted based on the specific requirements of different display regions and scanning speeds, allowing optimal signal timing while maintaining a relatively simple overall structure.
Solution Approach 2:
The invention changes the delay parameter of the shift register output signals. By adjusting the delay amount as a controllable parameter, the system can optimize signal timing for different scanning scenarios without fundamentally changing the shift register structure, thus controlling signal delay effectively while keeping device complexity low.
Data Source
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AI summary
The present disclosure provides a shift register, including an input circuit, a hold circuit, an output selection circuit, a first output circuit, a second output circuit, and a third output circuit. The input circuit is configured to control a voltage of a first node and a voltage of a second node. The hold circuit is configured to hold the voltage of the first node and the voltage of the second node as well as an output voltage of the first output circuit and an output voltage of the second output circuit. The output selection circuit is configured to select the first output circuit and/or the second output circuit to output a scanning signal, and control a voltage of a third node and/or a voltage of a fourth node based on the voltage of the second node. The first output circuit is configured to output a first output signal from a first output terminal based on the voltage of the first node and the voltage of the third node. The second output circuit is configured to output a second output signal from a second output terminal based on the voltage of the first node and the voltage of the fourth node. The third output circuit is configured to output a third output signal from a third output terminal based on a second clock signal and the voltage of the second node.