Display Substrate Shift-Register Packing for Narrow High-Resolution Displays
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Solution Overview
Problem
Related display products struggle to achieve narrow bezels while maintaining high resolution due to limited layout space for shift register units as pixel pitch decreases.
Innovation Solution
A display substrate design with a shift register unit that includes multiple signal lines arranged in a specific configuration, where the ratio of signal line widths to the unit width and pixel pitch value is optimized to be between 18 um and 40 um, allowing for efficient use of space and enabling narrow bezels in high-resolution displays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If pixel resolution is increased and pixel pitch is reduced, then display quality is improved, but layout space for shift register unit is reduced
Solution Approach 1:
The patent applies multi-layer stacking to arrange signal lines in three-dimensional space rather than confined to a single plane. By distributing signal lines across multiple conductive layers, the design achieves high signal line density without increasing the two-dimensional footprint, thus maintaining narrow bezels while supporting high pixel resolution
Solution Approach 2:
The patent implements nested arrangement where signal lines are organized in hierarchical layers within the shift register unit. Multiple signal lines are stacked vertically and arranged in sequences, creating a compact nested structure that maximizes space utilization in the limited bezel area
2Area of stationary object
If multiple signal lines are arranged in one shift register unit, then space utilization is improved, but manufacturing complexity increases
Solution Approach 1:
The patent divides the shift register unit into multiple sequences, with each sequence containing a specific number of signal lines (e.g., first sequence with first number of signal lines, second sequence with second number of signal lines). This segmentation allows systematic organization and simplifies the manufacturing process by breaking down the complex arrangement into manageable segments
3Length of stationary object
If signal line width ratio is optimized, then bezel width is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The patent optimizes the width ratio of signal lines to the shift register unit width, controlling it within a specific range (0.2 ≤ W1/W2 < 0.8). By adjusting this critical parameter, the design achieves narrow bezels while maintaining manufacturability. The patent further specifies that the width difference between adjacent signal lines should be within 10% to balance space utilization with manufacturing feasibility
Data Source
AI summary
A display substrate includes a base substrate including a display area and a peripheral area on at least one side of the display area; a pixel array, located in the display area and including multiple pixel units; and, a scan driving module, located in a driving circuit area of the peripheral area, and including multiple shift register units, multiple signal lines being arranged in one shift register units, and extending along a first direction; wherein a ratio of a sum W1 of widths of the multiple signal lines in a second direction to a width W2 of the shift register unit in the second direction is W1/W2, and a length of at least one pixel unit along the first direction is a pixel pitch value; the first direction intersects the second direction; a product of W1/W2 and the pixel pitch value is greater than 18 um and less than 40 um.